# ASIC Physical Design and Timing Engineer - New College Grad 2026

**Company**: NVIDIA
**Location**: Santa Clara, CA
**Experience**: entry
**Job type**: full-time
**Category**: Engineering
**Industry**: Technology

**Apply**: https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/ASIC-Physical-Design-and-Timing-Engineer---New-College-Grad-2026_JR2019810?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_d44ad7aa-a84

## Description

NVIDIA is seeking a motivated ASIC Timing Engineer to join its dynamic team. The engineer will drive physical design and timing analysis and closure of NVIDIA's GPUs, CPUs, DPUs, and SoCs at various levels.

**Key Responsibilities:**

- Drive physical design and timing analysis and closure of NVIDIA's GPUs, CPUs, DPUs, and SoCs at block level, cluster level, and/or full chip level.

- Help drive frontend and backend implementation, including synthesis, equivalence checking, floor-planning, timing constraints, timing and power convergence, and ECO implementation.

- Play a pivotal role in the success of innovative projects and advancement of NVIDIA's technology, working in a cross-functional environment interacting with multiple teams.

**Requirements:**

- Master's degree or higher in Electrical or Computer Engineering (or equivalent experience).

- Proficiency in Timing and Static Timing Analysis (STA).

- Hands-on experience in full-chip/sub-chip STA and timing convergence, timing constraints generation and management.

- Expertise with industry-standard EDA and timing convergence tools.

**Preferred Qualifications:**

- Proven experience in timing convergence for ASICs, CPUs, GPUs, or Network processors.

- Knowledge of deep sub-micron process nodes.

- Proficiency in AI/LLM and programming languages.

- Experience in physical design and optimization (e.g., synthesis, floorplanning, placement, CTS, routing, power) is a plus.

NVIDIA offers highly competitive salaries and a comprehensive benefits package, including equity and benefits.

## Skills

### Required
- Electrical or Computer Engineering
- Timing and Static Timing Analysis (STA)
- EDA tools

### Nice to have
- ASICs
- CPUs
- GPUs
- Network processors
- deep sub-micron process nodes
- AI/LLM
- physical design and optimization

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Source: [Apply at nvidia.wd5.myworkdayjobs.com](https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/ASIC-Physical-Design-and-Timing-Engineer---New-College-Grad-2026_JR2019810?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)