# Layout Design, Sr Engineer

**Company**: Synopsys
**Location**: Hyderabad
**Work arrangement**: onsite
**Experience**: senior
**Job type**: full-time
**Category**: Engineering
**Industry**: Technology
**Ticker**: SNPS
**Wikidata**: https://www.wikidata.org/wiki/Q2303478

**Apply**: https://careers.synopsys.com/job/hyderabad/layout-design-sr-engineer/44408/93979726464
**Canonical**: https://yubhub.co/jobs/job_d0d01c2f-b91

## Description

Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.

You are a dedicated and meticulous Layout Design Engineer with a passion for semiconductor technology. Your expertise lies in the intricate world of IC layout, and you thrive in environments that demand precision, creativity, and innovation.

Designing and developing standard cell layouts, ranging from simple (INV, ND, NR) to complex cells (Level Shifters, Flip Flops, Multi-bit combinational, Multi-bit Flip Flop cells) within the Logic Libraries IP team.

Developing cells across planar, CMOS, FinFet, GAA, uni-directional and multi-directional routing technologies, adapting to both native and cutting-edge platforms.

Applying comprehensive sign-off checks (DRC/LVS/ERC/ANT/DFM) to optimize manufacturability, performance, and yield across multiple foundries.

Collaborating with global teams, circuit design, CAD, and PD teams to resolve methodology issues and implement optimized layout designs.

Conducting design reviews and offering constructive feedback to enhance quality and performance.

Utilizing Unix/Shell/Python/TCL/ICV scripting to automate design workflows, QA checks, checklist enforcement, and quality metrics generation.

Accelerating the creation and optimization of high-performance logic library IP for next-generation silicon solutions.

Ensuring robust manufacturability and yield, contributing to the reliability and success of Synopsys' IP products.

Enhancing productivity and efficiency through workflow automation and quality assurance initiatives.

Driving innovation by implementing advanced layout techniques for emerging technologies like FinFet and GAA.

Fostering collaboration across global teams, leading to improved methodologies and best practices.

Maintaining the highest standards of quality, compliance, and performance in every design delivered.

## Skills

### Required
- BTech/MTech in Electrical Engineering, Electronics, or related field
- 2+ years of relevant experience in IC layout design, preferably in standard cell libraries
- Proficiency with Synopsys Custom Compiler, Virtuoso, Innovus/ICC2, and ICV/Calibre (DRC/LVS/DFM)
- Hands-on experience with TSMC, Samsung, UMC, and GlobalFoundries PDKs
- Strong scripting skills in Python, Tcl, Perl, SKILL, ICV, and shell scripting