# Sr Staff Engineer, FE-DFT and Timing Closure

**Company**: Synopsys
**Location**: Tokyo
**Experience**: staff
**Job type**: full-time
**Category**: Engineering
**Industry**: Technology
**Ticker**: SNPS
**Wikidata**: https://www.wikidata.org/wiki/Q2303478

**Apply**: https://careers.synopsys.com/job/tokyo/sr-staff-engineer-fe-dft-and-timing-closure/44408/102857902432?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_cfffe641-374

## Description

You are a front-end engineer who actually understands DFT, not just at the handoff level, but deep enough to know why a scan chain fails, why a compression ratio tanks, or why an ATPG tool chokes on certain RTL constructs.

At Synopsys, you will work with customers who need someone who can bridge the gap between front-end design intent and back-end DFT reality. What you build, guide, and standardize will determine whether their R2G flows actually work when it matters.

### What You'll Be Doing

- Lead front-end design and DFT methodology development for customer SoC programs, ensuring RTL design decisions support robust DFT insertion and R2G flow execution

- Work directly with front-end design teams to establish DFT-aware coding practices, hierarchy planning, clock architecture, and constraint definitions that enable clean scan insertion and test coverage

- Deploy and support DFT implementation flows including scan insertion, compression, ATPG, and boundary scan across multiple customer programs

- Serve as the technical bridge between front-end design teams and back-end DFT, implementation, and verification teams, translating issues and requirements in both directions

- Debug complex DFT failures that trace back to RTL design decisions, tool interpretation differences, or constraint mismatches, and drive resolution across teams

- Develop and standardize R2G flow methodologies that integrate front-end design quality checks with DFT readiness and back-end implementation requirements

- Support risk mitigation and schedule recovery for programs where front-end and DFT integration issues are blocking progress

### The Impact You Will Have

- Customer R2G flows execute cleanly because the front-end design was built with DFT requirements baked in from the start, not bolted on later

- DFT insertion and ATPG convergence accelerates across programs because you caught and fixed RTL issues that would have caused failures weeks downstream

- Front-end teams adopt DFT-aware design practices that prevent entire classes of scan, compression, and timing issues from ever appearing

- Cross-functional teams resolve front-end and DFT integration problems faster because you can speak both languages and translate the real issue

- Program schedules stay on track because you identified where the RTL and DFT flow were misaligned and built a methodology fix that worked

- Synopsys R2G flows and best practices improve because you fed real customer pain points back with enough technical depth to drive methodology and product enhancements

### What You'll Need

- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or equivalent practical experience in SoC design

- 10+ years of hands-on experience in front-end RTL design, with significant exposure to DFT implementation, scan insertion, ATPG, or test methodology

- Strong understanding of DFT concepts including scan chains, compression, ATPG, boundary scan, and how RTL design decisions impact test coverage and flow execution

- Proven ability to debug complex issues that span front-end design, DFT insertion, and back-end implementation, often involving multiple EDA tools

- Experience developing or deploying R2G flows that integrate front-end design quality, DFT readiness, and back-end implementation requirements

- Ability to work across cross-functional teams and communicate technical issues clearly to both design and DFT engineers

- Experience working directly with customers or internal product development teams in a technical lead or applications engineering capacity is a strong plus

## Skills

### Required
- front-end RTL design
- DFT implementation
- scan insertion
- ATPG
- test methodology
- R2G flows
- SoC design
- Electrical Engineering
- Computer Engineering

### Nice to have
- debugging complex issues
- cross-functional teams
- technical lead
- applications engineering

---

Source: [Apply at careers.synopsys.com](https://careers.synopsys.com/job/tokyo/sr-staff-engineer-fe-dft-and-timing-closure/44408/102857902432?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)