# Principal ASIC Verification Engineer **Company**: Hewlett Packard Enterprise **Location**: Sunnyvale, CA **Work arrangement**: hybrid **Experience**: senior **Job type**: full-time **Salary**: Annual Salary USD 181,000 - 367,000 **Category**: Engineering **Industry**: Technology **Apply**: https://hpe.wd5.myworkdayjobs.com/en-US/Jobsathpe/job/Sunnyvale-California-United-States-of-America/Principal-ASIC-Verification-Engineer_1211207-2?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply **Canonical**: https://yubhub.co/jobs/job_ce87af31-57b ## Description We are seeking a highly motivated Senior ASIC Verification Engineer to join our networking silicon development team. As part of our fast-paced silicon group, you will become an expert in building high-speed ASICs, from specifications to final netlist. We give you opportunities to work on complex modules and subsystems where you can challenge yourself and grow. **Key Responsibilities:** - Own and drive block-level or subsystem verification efforts, from creating test plans to achieving comprehensive coverage closure. - Develop, enhance, and maintain advanced UVM verification environments, including agents, sequences, scoreboards, virtual sequences, and register models. - Perform constraint-driven random testing, debug complex SoC designs, and ensure functional coverage and assertion goals are met. - Analyze simulation results using industry-leading simulation tools (e.g., Cadence Xcelium, Synopsys VCS, Mentor Questa) and debug waveforms to validate design functionality. - Collaborate with cross-functional teams to identify and resolve issues, ensuring high-quality ASIC/SoC deliverables. **Required Skills and Qualifications:** - 15+ years of experience in ASIC/SoC verification with a proven track record of owning verification from test plan to coverage closure. - Strong expertise in SystemVerilog and UVM methodology, including developing environments from scratch. - Deep understanding of randomization, constraints, functional coverage, and assertions (SVA). - Hands-on experience in test planning, coverage analysis, and debugging of complex SoC designs. - Proficiency with industry-standard simulation tools (e.g., Cadence Xcelium, Synopsys VCS, Mentor Questa) and waveform debugging. **Preferred Skills and Experience:** - Experience verifying networking ASICs or router datapath/control blocks, such as packet processing, forwarding engines, or fabric interfaces. - Familiarity with high-speed interconnects, buffers, or scheduling pipelines in large networking SoCs. - Exposure to emulation environments, hardware acceleration, or traffic-model integration. - Knowledge of coverage analytics, regression dashboards, and continuous-integration flows (e.g., Jenkins). - Understanding of low-power (UPF) or formal verification methodologies. - Experience with post-silicon bring-up and debug is a plus. - Familiarity with emulation environments and debug flows is desirable. **What We Can Offer You:** - Health & Wellbeing: We strive to provide our team members and their loved ones with a comprehensive suite of benefits that supports their physical, financial and emotional wellbeing. - Personal & Professional Development: We also invest in your career because the better you are, the better we all are. - Unconditional Inclusion: We are unconditionally inclusive in the way we work and celebrate individual uniqueness. ## Skills ### Required - ASIC/SoC verification - SystemVerilog - UVM methodology - randomization - constraints - functional coverage - assertions (SVA) - test planning - coverage analysis - debugging ### Nice to have - networking ASICs - router datapath/control blocks - high-speed interconnects - buffers - scheduling pipelines - emulation environments - hardware acceleration - traffic-model integration - coverage analytics - regression dashboards - continuous-integration flows - low-power (UPF) - formal verification methodologies --- Source: [Apply at hpe.wd5.myworkdayjobs.com](https://hpe.wd5.myworkdayjobs.com/en-US/Jobsathpe/job/Sunnyvale-California-United-States-of-America/Principal-ASIC-Verification-Engineer_1211207-2?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)