# Layout Design, Staff Engineer

**Company**: Synopsys
**Location**: Da Nang, Vietnam
**Work arrangement**: onsite
**Experience**: staff
**Job type**: full-time
**Salary**: Competitive salaries
**Category**: Engineering
**Industry**: Technology
**Ticker**: SNPS
**Wikidata**: https://www.wikidata.org/wiki/Q2303478

**Apply**: https://careers.synopsys.com/job/da-nang/layout-design-staff-engineer-in-da-nang/44408/96039332752?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_cb9b4a91-c08

## Description

Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.

The ideal candidate has spent years in the trenches of memory layout, where a single transistor out of place can mean the difference between a chip that ships and one that doesn't. SRAM, ROM, eDRAM, you know these structures at the cell level, not just conceptually but in the way you know a tool you have used every day for years.

As a staff engineer, you will lead physical layout design for advanced memory IP including SRAM, ROM, and eDRAM at the cell, array, and peripheral circuit levels. You will ensure every layout meets foundry process design rules and memory-specific constraints, resolving DRC and LVS issues with precision.

Key responsibilities include:

- Leading physical layout design for advanced memory IP

- Ensuring layouts meet foundry process design rules and memory-specific constraints

- Optimizing layouts for area efficiency, performance targets, power consumption, yield improvement, and manufacturability

- Performing RC extraction and parasitic analysis on dense memory arrays

- Debugging complex layout issues

- Collaborating with circuit designers, verification engineers, and process teams

The impact you will have includes delivering memory IP that powers chips for AI, mobile, automotive, and high-performance computing at leading tech companies, reducing risk and accelerating time to market with layouts that are correct, optimized, and manufacturable before tapeout, and driving innovation in layout techniques and automation that improve efficiency and quality across the memory IP portfolio.

Requirements include a bachelor's or master's degree in electronics engineering, telecommunications, physics, or a related technical field, at least 5 years of hands-on experience in custom layout design with significant focus on memory structures like SRAM, ROM, or eDRAM, deep expertise in memory layout at the transistor and cell level, and proficiency with layout tools such as Custom Compiler, Virtuoso, or IC Compiler for physical design and verification.

## Skills

### Required
- custom layout design
- memory structures
- SRAM
- ROM
- eDRAM
- foundry process design rules
- memory-specific constraints
- DRC
- LVS
- RC extraction
- parasitic analysis
- layout optimization
- area efficiency
- performance targets
- power consumption
- yield improvement
- manufacturability

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Source: [Apply at careers.synopsys.com](https://careers.synopsys.com/job/da-nang/layout-design-staff-engineer-in-da-nang/44408/96039332752?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)