# Senior Software R&D Engineer, VLSI Physical Design

**Company**: NVIDIA
**Location**: Santa Clara, CA
**Experience**: senior
**Job type**: full-time
**Category**: Engineering
**Industry**: Technology

**Apply**: https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-Software-R-D-Engineer--VLSI-Physical-Design_JR2015155?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_cae7ad5b-719

## Description

NVIDIA's success builds on a foundation of industry-leading hardware. We achieve distinction through extensive design optimization, including combining the best of external EDA with highly optimized, internal EDA tools.

We are seeking a Senior R&D Software Engineer with proven experience in multiple areas of VLSI Physical Design Algorithms (sizing, buffering, CTS, legalization, incremental place and route etc.). Understanding both software and hardware aspects is key. Creativity and self-drive to explore and perfect fast, high-capacity software are required.

**Responsibilities:**

- Invent new optimization engines that fuse traditionally independent engines (e.g., co-optimization of legalization and sizing) with the objective of increasing chip frequency while minimizing power consumption across a suite of internal optimization tools.

- Improve algorithms (in C++) for gate-level sizing, buffering, useful clock skew, cell legalization, power minimization, ECO routing, and incremental parasitic extraction.

- Own the whole process from discovery and invention of new optimization opportunities, to developing solutions and working directly inside design teams to facilitate deployment.

**Requirements:**

- BS, MS, PhD or equivalent experience in Electrical Engineering or Computer Science

- 6+ years in VLSI algorithms development using C++

- Strong understanding of VLSI timing optimization and related concepts, including cell libraries, interconnect models, crosstalk, glitches, IR drop, timing constraints, corners, congestion, etc.

- Familiarity with design implementation tools such as ICC2, Innovus, PrimeTime, Tempus, and StarRC and typical design flows written in Perl, Tcl, and Python

- Strong communication and interpersonal skills

**Preferred Qualifications:**

- C++14 or newer experience, such as lambdas and concurrency

- Detailed understanding of how multiple Physical Design steps interact and how they can potentially be fused together to form hybrid engines that result in better PPA

- Experience in high-performance software design including multithreading, distributed computing, efficient memory and I/O use, etc.

- Highly driven to craft outstanding software towards improving PPA with a dedication to continuous improvement

- Experience with reinforcement learning, GNNs (Graph Neural Networks), and other relevant machine learning frameworks, especially as applied to physical design

## Skills

### Required
- C++
- VLSI Physical Design
- Electrical Engineering
- Computer Science
- EDA tools

### Nice to have
- C++14
- multithreading
- distributed computing
- reinforcement learning
- GNNs

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Source: [Apply at nvidia.wd5.myworkdayjobs.com](https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-Software-R-D-Engineer--VLSI-Physical-Design_JR2015155?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)