# SOC Engineering Intern

**Company**: Synopsys
**Location**: Yerevan
**Job type**: internship
**Category**: Engineering
**Industry**: Technology
**Ticker**: SNPS
**Wikidata**: https://www.wikidata.org/wiki/Q2303478

**Apply**: https://careers.synopsys.com/job/yerevan/soc-engineering-intern/44408/102879324064?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/job/soc-engineering-intern-caa0a216-0ea/

## Description

Our internship programs offer real-world projects, hands-on experience, and opportunities to collaborate with passionate teams globally.

You will join a dynamic and highly skilled engineering team focused on delivering world-class ASIC and SoC solutions.

**What You'll Be Doing:**

- Supporting chip-level physical design activities from netlist through final implementation (RTL to GDSII)

- Gaining hands-on experience with key physical design stages, including floorplanning, placement, clock tree synthesis, routing, and physical verification

- Assisting with design optimization for timing, power, area, and congestion

- Contributing to debugging design or flow issues under guidance from senior engineers

- Supporting the development and improvement of automation scripts and design methodologies

- Learning to investigate and troubleshoot design, tool, and flow-related issues throughout the implementation cycle

- Participating in technical discussions, reviews, and knowledge-sharing activities within the team

**What You'll Need:**

- Currently pursuing a Bachelor's or Master's Degree in Electrical Engineering, Computer Engineering, Microelectronics, or a related field

- Basic understanding of digital design, semiconductor fundamentals, and/or ASIC design concepts

- Familiarity with the ASIC physical design flow or concepts such as floorplanning, placement, clock tree synthesis, routing, and timing analysis is a plus

- Basic understanding of timing, power, and physical verification concepts is beneficial

- Exposure to EDA tools or physical design tools through coursework, university projects, or previous experience is a plus

- Familiarity with scripting or programming languages such as TCL, Python, Perl, or similar is an advantage

- Good written and verbal communication skills in English

- Eagerness to learn, collaborate, and develop practical engineering skills in a professional environment

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## Skills

### Required
- Electrical Engineering
- Computer Engineering
- Microelectronics
- ASIC design
- digital design
- semiconductor fundamentals

### Nice to have
- ASIC physical design flow
- floorplanning
- placement
- clock tree synthesis
- routing
- timing analysis
- EDA tools
- physical design tools
- TCL
- Python
- Perl

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Source: [Apply at careers.synopsys.com](https://careers.synopsys.com/job/yerevan/soc-engineering-intern/44408/102879324064?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)