# Physical Design Technical Leader

**Company**: Cisco
**Location**: Pune, India
**Experience**: senior
**Job type**: full-time
**Category**: Engineering
**Industry**: Technology

**Apply**: https://cisco.wd5.myworkdayjobs.com/en-US/Cisco_Careers/job/Pune-India/Physical-Design-Technical-Leader---ASIC-SoC-physical-design_2030618?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/job/physical-design-technical-leader-ca817717-896/

## Description

Cisco's Silicon One Optics Group (S1O) designs and delivers high-speed optical transceivers and platforms that power Cisco's core data center networking solutions. You will work with Cisco's best-in-class Silicon Photonics team to drive the development and optimization of optical transceivers and modules that seamlessly integrate with Cisco's routing, switching, and datacenter platforms.

As a Physical Design Technical Leader, you will guide the engineering team and drive physical implementation for Cisco's next-generation silicon photonics driver and receiver ICs, powering 100G, 200G, and 400G-per-lambda Co-Packaged Optics (CPO) and optical engine solutions. You will lead the physical design strategy and execution for high-performance silicon integrating sophisticated digital control logic, CPU subsystems, high-speed standard interfaces (UCIe), and ultra-fast transmit/receive data-paths in groundbreaking process nodes (TSMC sub-5nm/3nm/2nm).

Key responsibilities:

- Lead, mentor, and technically steer a team of physical design engineers, driving task allocations, schedule tracking, and design reviews.

- Own full-chip and hierarchical block-level RTL-to-GDSII implementation and sign-off on advanced nodes.

- Architect robust, automated backend flows to boost team productivity and tapeout predictability.

- Serve as the primary physical design communicator with Analog Design, Custom Layout, Package Co-Design, and Foundry partners.

Minimum qualifications:

- Bachelor’s degree or equivalent experience in electrical engineering, Electronics & Communication or related field with minimum 12+ years of Industry experience.

- 8+ years of physical design (PD) experience delivering ASIC/SoC designs in sophisticated CMOS technology nodes (7nm/5nm/3nm/2nm).

- Proven experience driving the full RTL-to-GDSII flow at block and/or full-chip level.

- Strong proficiency with industry-standard EDA tools.

- Strong scripting proficiency in Tcl, Python, Bash, or Perl for flow automation.

Preferred qualifications:

- Education: Master's degree (M.S. / M.Tech) in Electrical Engineering, VLSI Design, or Microelectronics.

- Experience: 12-15+ years of ASIC/SoC physical implementation experience with multiple successful tape-outs in ground-breaking process nodes.

- Technical Team Leadership: Consistent record of leading physical design project execution.

- Mixed-Signal & High-Speed IP Integration: Strong experience handling floorplanning and noise isolation for sensitive mixed-signal macros.

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## Skills

### Required
- physical design
- ASIC/SoC design
- CMOS technology
- EDA tools
- scripting

### Nice to have
- mixed-signal macro design
- high-speed IP integration
- floorplanning
- noise isolation

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Source: [Apply at cisco.wd5.myworkdayjobs.com](https://cisco.wd5.myworkdayjobs.com/en-US/Cisco_Careers/job/Pune-India/Physical-Design-Technical-Leader---ASIC-SoC-physical-design_2030618?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)