# SOC Engineering, Principal Engineer **Company**: Synopsys **Location**: Bengaluru **Work arrangement**: onsite **Experience**: senior **Job type**: full-time **Category**: Engineering **Industry**: Technology **Ticker**: SNPS **Wikidata**: https://www.wikidata.org/wiki/Q2303478 **Apply**: https://careers.synopsys.com/job/bengaluru/soc-engineering-principal-engineer/44408/95590601056?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply **Canonical**: https://yubhub.co/jobs/job_c94c85ec-5df ## Description Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. You are a passionate and driven STA Expert with a strong technical leadership and execution skills in Static Timing Analysis and design timing & power closure flows and methodologies. You have a proven ability to lead and deliver complex designs to tapeout. With at least 12 years of hands-on experience in advanced technology nodes such as 7nm, 5nm, or even 3nm, you thrive in fast-paced, innovative environments and are eager to tackle new technical challenges. Your expertise spans the entire timing closure spectrum,from constraints development, validation, static timing analysis (STA), power analysis, Timing & power ECO generation. You may also have good understanding and working experience of synthesis, and Formal verification. You have experience in both block-level and full-chip expertise, and you’re adept at developing and validating timing constraints and closing timing on aggressive schedules. Your toolset includes industry-leading Synopsys solutions like PrimeTime, PrimePower, PT-PX, PrimeClosure, Tweaker allowing you to deliver optimal solutions for high-frequency, low-power designs. Beyond your technical skills, you are a collaborative team player who communicates effectively across global teams, valuing diversity of thought and experience. You are motivated by problem-solving, have a keen analytical mindset, and are always seeking opportunities to automate and optimize workflows using Python, PERL, TCL, or other scripting languages. You take ownership of your work and pride yourself on delivering high-quality, robust solutions that drive organisational success. Responsibilities: - Independently own and drive signoff static timing analysis and timing closure for advanced process nodes (7nm/5nm/3nm), ensuring successful tape-outs. - Execute static timing analysis (STA), power analysis, synthesis and timing/power closure to meet stringent performance and power targets. - Develop and validate timing constraints at block-level or Full SoC level. - Collaborate with cross-functional teams across geographies to resolve complex design challenges and ensure design quality and schedule adherence. - Utilize and optimize Synopsys EDA tools, including PrimePower, PT-PX, PrimeClosure, and Tweaker to deliver state-of-the-art silicon solutions. - Develop and maintain automation scripts in Python, PERL, TCL, or other relevant languages to streamline design flows and improve efficiency. - Contribute to the continuous improvement of static timing analysis flows and methodologies and best practices, sharing insights and mentoring junior engineers as needed. Impact: - Accelerate the delivery of high-performance, low-power silicon solutions that power next-generation technology platforms worldwide. - Enable Synopsys customers to achieve first-pass silicon success through robust and innovative physical design implementations. - Drive technical excellence and best practices within the team, influencing the future direction of static timing analysis and timing closure methodologies at Synopsys. - Foster a collaborative and inclusive culture by working seamlessly with global teams and sharing technical expertise. - Contribute to Synopsys’ leadership in EDA tools adoption, providing valuable feedback to enhance product offerings and customer satisfaction. - Support strategic customer engagements and help expand Synopsys' presence in the semiconductor ecosystem through successful project outcomes. Requirements: - Bachelor’s or Master’s degree (BE/BTech/MTech or equivalent) in Electronics, Electrical Engineering, or a related field. - 12+ years of relevant experience in static timing analysis, particularly in advanced technology nodes (7nm/5nm/3nm). - Comprehensive hands-on experience of constraints development, validation, static timing analysis (STA), power analysis, Timing and power ECO generation. - Proficiency with Synopsys EDA tools such as PrimeTime, PT-PX, PrimeClosure, Tweaker. - Working experience with Synopsys tools like Fusion Compiler, Design Compiler, Formality, and StarRC. - Strong scripting and automation skills using Python, PERL, TCL, or similar languages. - Solid understanding of timing constraints development, validation, static timing analysis and closure, for both block-level and full-chip designs. - Exposure to high-frequency design and low-power design methodologies. Who You Are: - Proactive, self-motivated, and driven to achieve technical excellence. - Exceptional problem-solving and analytical skills with a keen attention to detail. - Excellent communication and interpersonal abilities, comfortable working in diverse and global teams. - Collaborative team player who values knowledge sharing and mentoring others. - Adaptable and open to learning new technologies and methodologies in a rapidly evolving field. Team You’ll Be A Part Of: - You’ll join a world-class team of backend and static timing analysis engineers at Synopsys, dedicated to delivering innovative system design solutions for our global customers. Our team thrives on collaboration, technical excellence, and a shared passion for pushing the boundaries of semiconductor design. Working closely with experts across multiple domains, you will play a key role in empowering customers to achieve their silicon goals while contributing to Synopsys’ leadership in the industry. Rewards and Benefits: - We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. ## Skills ### Required - Static Timing Analysis - Design Timing & Power Closure Flows and Methodologies - Constraints Development - Validation - Synthesis - Formal Verification - Python - PERL - TCL - Scripting Languages - Timing Constraints Development - Static Timing Analysis and Closure - High-Frequency Design - Low-Power Design Methodologies --- Source: [Apply at careers.synopsys.com](https://careers.synopsys.com/job/bengaluru/soc-engineering-principal-engineer/44408/95590601056?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)