# ASIC Digital Verification, Sr. Manager

**Company**: Synopsys
**Location**: Mississauga, Ontario
**Experience**: senior
**Job type**: full-time
**Salary**: $166000-$248000
**Category**: Engineering
**Industry**: Technology
**Ticker**: SNPS
**Wikidata**: https://www.wikidata.org/wiki/Q2303478

**Apply**: https://careers.synopsys.com/job/mississauga/asic-digital-verification-sr-manager/44408/101724603584?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_c8eac0ff-482

## Description

You will be a Senior Manager in the ASIC Digital Verification team at Synopsys, a leading provider of semiconductor solutions. You will lead a team and guide them towards the closure of day-to-day verification activities.

**Job Description**

You are a seasoned professional with a robust background in the design and verification of IP cores and/or SOC. You have a strong command of Verilog/SystemVerilog and are experienced in developing and managing testbenches in UVM environments.

**Responsibilities**

- Specify, design, architect, and implement Digital Verification environments for next-generation SERDES PHY IP solutions.

- Lead a team, guiding them towards the closure of day-to-day verification activities.

- Work closely with RTL designers, Architects, and Verification Engineers as part of a global team.

- Understand design specifications and develop test plans and testbenches at both unit and system levels.

- Ensure product release milestones are met through effective regression debug triaging and verification activities.

- Contribute to the development and implementation of next-generation SERDES PHY IP solutions, fostering a culture of continuous improvement and innovation.

**Requirements**

- BS/MS in EE/EC/VLSI with 15+ years of relevant experience in the verification of IP cores and/or SOC.

- Experience in leading a team of engineers and guiding them towards achieving project milestones.

- Hands-on experience in verification of complex designs at the IP or SoC level.

- Strong knowledge of Verilog/SystemVerilog and experience in developing testbenches in UVM environments.

- Proficiency in Perl/Python-based automation and excellent communication and problem-solving skills.

- Understanding the PCIe and Ethernet standards is a plus.

**Benefits**

- Comprehensive medical and healthcare plans that work for you and your family.

- In addition to company holidays, we have ETO and FTO Programs.

- Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.

- Purchase Synopsys common stock at a 15% discount, with a 24-month look-back.

- Save for your future with our retirement plans that vary by region and country.

- Competitive salaries.

## Skills

### Required
- Verilog
- SystemVerilog
- UVM
- Perl
- Python
- PCIe
- Ethernet

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Source: [Apply at careers.synopsys.com](https://careers.synopsys.com/job/mississauga/asic-digital-verification-sr-manager/44408/101724603584?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)