# Senior Memory Mask Design Engineer

**Company**: NVIDIA
**Location**: Bengaluru
**Work arrangement**: onsite
**Experience**: senior
**Job type**: full-time
**Category**: Engineering
**Industry**: Technology

**Apply**: https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-Memory-Mask-Design-Engineer_JR2016231?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_c6cdc33c-d4b

## Description

We are looking for a Senior Digital/Memory Mask Design Engineer to join our growing team of diverse individuals responsible for handling challenging high-speed digital memory circuit designs.

As an NVIDIAN, you'll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our team and see how you can make a lasting impact on the world!

**Responsibilities:**

- Implement IC layout of innovative, high-performance, high-speed CMOS integrated circuits in foundry CMOS process nodes in 3nm, 5nm, 7nm and lower nodes following industry standard methodologies.

- Lead the architecture and layout design of key memory subsystems, including control logic, sense amplifiers, I/O blocks, bit-cell arrays, and decoders for advanced technology nodes.

- Direct custom layout and verification of complex memory cells, setting standards and methodologies for compiler-driven design flows.

- Be responsible for and optimize all physical verification activities, including DRC, LVS, density analysis, and comprehensive tape-out checks.

- Drive the identification and resolution of complex physical design issues in compiler-generated layouts, mentoring junior engineers in established methodologies.

- Provide guidance on IR drop and EM mitigation strategies, establishing design methodologies for robust memory layouts.

- Possess deep expertise in ultra-deep sub-micron layout challenges, regularly innovating and implementing advanced solutions.

- Development of memory compilers, leading solving efforts and driving optimization for performance, area, and manufacturability.

- Cultivate effective teamwork across multi-functional teams, influencing project direction and ensuring alignment with organizational objectives.

- Excel in resource management, representing the team in technical discussions with customers

**Requirements:**

- B.E/B Tech./M Tech in Electronics or equivalent experience with 6+ years of proven experience in Memory layout in advanced CMOS process.

- Detailed knowledge of industry standard EDA tools for Cadence.

- Experience with layout of high-performance memories of various types.

- Knowledge of Layout basics including the various types of bitcells, Decoder, LIO etc. (matching devices, symmetrical layout, signal shielding)

- Experience with floor planning, block level routing and macro level assembly.

- Detailed knowledge of top level verification including the EM/IR quality checks and detailed knowledge of layout dependent effects including LOD, Dummification, fills etc.

## Skills

### Required
- Cadence
- EDA tools
- Memory layout
- High-performance memories
- Layout basics
- Floor planning
- Block level routing
- Macro level assembly
- Top level verification
- EM/IR quality checks
- Layout dependent effects

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Source: [Apply at nvidia.wd5.myworkdayjobs.com](https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-Memory-Mask-Design-Engineer_JR2016231?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)