# Senior Digital Design Verification Engineer - Hardware

**Company**: NVIDIA
**Location**: Hsinchu
**Work arrangement**: onsite
**Experience**: senior
**Job type**: full-time
**Category**: Engineering
**Industry**: Technology

**Apply**: https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/Taiwan-Hsinchu/Senior-Digital-Design-Verification-Engineer---Hardware_JR2015759?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_c67169e9-b93

## Description

We're now looking for a Senior Digital Design Verification Engineer to verify the design and implementation of our cutting-edge SerDes IPs. As a member of our team, you'll work on delivering IPs that will be consumed by standard as well as industry-leading proprietary high-speed protocols. Your expertise in verification methodologies such as UVM and experience with SystemVerilog will be crucial in ensuring the correctness of our designs.

Responsibilities:

- Verify the digital design, golden models, and micro-architecture of the SerDes IPs using advanced verification methodologies such as UVM.

- Build reusable bus functional models, monitors, checkers, and scoreboards following coverage-driven verification methodology.

- Understand the design and implementation, define the verification scope, develop the verification infrastructure, and verify the correctness of the design.

- Write and execute test plans and thoroughly verify a design in a product shipment-focused/compressed schedule.

- Work with architects, designers, and pre- and post-silicon verification teams to accomplish your tasks.

Requirements:

- Bachelor's or Master's degree (or equivalent experience) in Electrical Engineering, Computer Science, or Computer Engineering.

- At least 5 years of proven experience.

- Background in verification at Unit/Sub-system/SOC level and expertise in SystemVerilog a must.

- Experience using random stimulus along with functional coverage and assertion-based verification methodologies a must.

- Experience in verification methodologies like UVM/VMM and exposure to industry-standard verification tools for simulation and debug.

Nice to Have:

- Expertise in bus or interconnect protocols (e.g., PCI Express, USB, SATA).

- Experience in verifying complex SerDes systems, understanding mixed-signal designs, and have experience in modeling of analog circuits.

- Perl, Python, C/C++ programming language experience.

- Good debugging and analytical skills.

- Good communication skills & dream to work as a great teammate.

## Skills

### Required
- SystemVerilog
- UVM
- Verification methodologies
- Random stimulus
- Functional coverage
- Assertion-based verification

### Nice to have
- Bus or interconnect protocols
- Complex SerDes systems
- Mixed-signal designs
- Analog circuit modeling
- Perl
- Python
- C/C++

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Source: [Apply at nvidia.wd5.myworkdayjobs.com](https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/Taiwan-Hsinchu/Senior-Digital-Design-Verification-Engineer---Hardware_JR2015759?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)