# Research Engineer, Chip Design RL

**Company**: Anthropic
**Location**: San Francisco, CA
**Work arrangement**: hybrid
**Experience**: senior
**Job type**: full-time
**Salary**: $500,000-$850,000 USD
**Category**: Engineering
**Industry**: Technology
**Wikidata**: https://www.wikidata.org/wiki/Q116758847

**Apply**: https://job-boards.greenhouse.io/anthropic/jobs/5459098008?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_c27e9129-1e4

## Description

Anthropic's mission is to create reliable, interpretable, and steerable AI systems that are safe and beneficial for users and society.

The Reinforcement Learning teams at Anthropic lead the company's reinforcement learning research and development, contributing to various AI models, including Claude.

As a Research Engineer in the Code RL team, you will advance our models' ability to design silicon by leveraging your chip design expertise and turning it into tasks and signals for models to learn from.

Responsibilities:

- Invent, design, and implement RL environments and evaluations for agentic RTL generation, design verification, and physical design optimization.

- Work on cross-cutting RL considerations such as EDA-tool latency optimization and proxy rewards.

- Conduct experiments and shape our roadmap.

- Deliver your work into research and production training runs.

- Collaborate with other researchers and engineers across and outside Anthropic.

Requirements:

- Expertise in ASIC or FPGA design: RTL, design verification, physical design, PPA optimization, DFT, ECOs.

- Fluency with industry EDA tools and processes.

- Experience with tape-out chips and going from spec to silicon.

- Ability to balance research exploration with engineering implementation.

- Passion for AI's potential and commitment to developing safe and beneficial systems.

Strong candidates may also have:

- Experience with reinforcement learning, evaluations, or environments.

- Built tooling or automation around chip design flows.

- Worked on ML accelerators or high-performance compute hardware.

- Familiarity with high-level synthesis or architecture simulators.

The annual compensation range for this role is $500,000-$850,000 USD.

Logistics:

- Minimum education: Bachelor’s degree or an equivalent combination of education, training, and/or experience.

- Required field of study: A field relevant to the role.

- Minimum years of experience: Correlates with internal job level requirements.

- Location-based hybrid policy: 25% office time.

- Visa sponsorship: Available.

Benefits:

- Competitive compensation.

- Optional equity donation matching.

- Generous vacation and parental leave.

- Flexible working hours.

- Lovely office space.

## Skills

### Required
- ASIC design
- FPGA design
- RTL
- design verification
- physical design
- PPA optimization
- DFT
- ECOs
- EDA tools
- chip design

### Nice to have
- reinforcement learning
- evaluations
- environments
- tooling
- automation
- chip design flows
- ML accelerators
- high-performance compute hardware
- high-level synthesis
- architecture simulators

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Source: [Apply at job-boards.greenhouse.io](https://job-boards.greenhouse.io/anthropic/jobs/5459098008?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)