# IP (PCIE/CXL/USB/DP) Subsystem Design Implementation Engineer

**Company**: Synopsys
**Location**: Shanghai
**Experience**: senior
**Job type**: employee
**Category**: Engineering
**Industry**: Technology
**Ticker**: SNPS
**Wikidata**: https://www.wikidata.org/wiki/Q2303478

**Apply**: https://careers.synopsys.com/job/shanghai/ip-pcie-cxl-usb-dp-subsystem-design-implementation-engineer/44408/92638132304
**Canonical**: https://yubhub.co/jobs/job_c01e313a-c5a

## Description

We're looking for an IP (PCIE/CXL/USB/DP) Subsystem Design Implementation Engineer to join our team.

Our high-speed interface IP (PCIE/CXL/USB/DP) subsystem solution is gradually becoming a key module of AI acceleration, GPGPU, Big-Data SOC chips. More and more customers have adopted our latest PCIE GEN6/GEN7 with CXL/IDE to improve security, reduce system latency, and meet the high bandwidth demands of high-end SOCs such as various cloud services, AI, and GPGPU.

Responsibilities:

* Implement IP (PCIE/CXL/USB/DP) subsystem design using synthesis, timing optimization, SDC writing, CDC/RDC checking, etc.
* Work with internal teams and customers to ensure successful integration and validation of the IP subsystem.
* Collaborate with cross-functional teams to develop and maintain design documentation, test plans, and other deliverables.

Requirements:

* Minimum 5+ years of experience in IP/ASIC/SOC design implementation.
* Hands-on experience in synthesis, timing optimization, SDC writing, CDC/RDC checking, etc.
* Domain understanding of one of the interface standards: PCIe, USB, Display Port, Ethernet, or DDR.
* Good communication skills while interacting with internal teams and customers.

Preferred Experience:

* Experience in Design Compiler, Fusion Compiler, PrimeTime, Spyglass, or VC Spyglass.
* Experience in DesignWare Core IPs or PHYs.
* Experience in TCL, Perl, Python, or other shell scripting.

Benefits:

* Competitive salary and benefits package.
* Opportunities for professional growth and development.
* Collaborative and dynamic work environment.

## Skills

### Required
- IP/ASIC/SOC design implementation
- synthesis
- timing optimization
- SDC writing
- CDC/RDC checking
- PCIe
- USB
- Display Port
- Ethernet
- DDR

### Nice to have
- Design Compiler
- Fusion Compiler
- PrimeTime
- Spyglass
- VC Spyglass
- DesignWare Core IPs
- PHYs
- TCL
- Perl
- Python
- shell scripting