# RTL Design Engineer

**Company**: Synopsys
**Location**: Boxborough, Massachusetts
**Work arrangement**: onsite
**Experience**: senior
**Job type**: full-time
**Salary**: $138000-$208000
**Category**: Engineering
**Industry**: Technology
**Ticker**: SNPS
**Wikidata**: https://www.wikidata.org/wiki/Q2303478

**Apply**: https://careers.synopsys.com/job/boxborough/rtl-design-engineer/44408/101381296240?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_bd958704-703

## Description

Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

You are a highly experienced digital design engineer with deep expertise in PHY architecture and RTL development. You bring a strong foundation in high-speed interface technologies such as DDR and UCIe, combined with hands-on experience delivering complex ASIC designs from concept through implementation.

## Responsibilities

- Architect, design, and develop high-performance digital logic for PHY, DDRIO, and UCIe-based solutions.

- Define and implement RTL architectures while working closely with verification, physical design, and system teams.

- Drive chip- and block-level design activities through all phases of the ASIC development cycle.

- Optimize designs for performance, power, area (PPA), and product scalability.

- Develop and evaluate complex physical IP solutions, including SERDES and DDR subsystems.

- Review designs and mentor engineers to ensure technical excellence and development best practices.

- Collaborate with cross-functional teams to deliver high-quality silicon solutions on schedule.

## The Impact You Will Have

- Enable next-generation high-speed connectivity solutions used in advanced semiconductor products.

- Influence architectural decisions that improve performance, power efficiency, and scalability.

- Contribute to industry-leading PHY and interface IP development.

- Drive innovation that strengthens Synopsys' leadership in semiconductor design solutions.

- Support technical growth across the engineering organization through collaboration and mentorship.

## Requirements

- BS in Electrical Engineering, Computer Engineering, or related field with 12+ years of relevant experience, or MS with 10+ years of experience.

- Strong experience in ASIC RTL design and digital logic development.

- Expertise in PHY design, DDRIO, UCIe, SERDES, or related high-speed interface technologies.

- Solid understanding of the complete SoC design cycle, from architecture through implementation.

- Experience with design verification methodologies and hardware debugging.

- Strong problem-solving, analytical, and communication skills.

## Benefits

- Comprehensive medical and healthcare plans

- Time away programs, including ETO and FTO

- Family support, including maternity and paternity leave, parenting resources, adoption and surrogacy assistance

- ESPP: purchase Synopsys common stock at a 15% discount

- Retirement plans that vary by region and country

## Skills

### Required
- ASIC RTL design
- digital logic development
- PHY design
- DDRIO
- UCIe
- SERDES
- SoC design cycle
- design verification methodologies
- hardware debugging

### Nice to have
- complex IPs for advanced process technologies
- low-power design techniques
- clocking architectures
- mentoring engineers
- leading technical projects
- industry-standard EDA tools
- design methodologies

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Source: [Apply at careers.synopsys.com](https://careers.synopsys.com/job/boxborough/rtl-design-engineer/44408/101381296240?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)