# ASIC Verification Engineering Intern

**Company**: Hewlett Packard Enterprise
**Location**: Roseville, California
**Work arrangement**: hybrid
**Job type**: full-time
**Salary**: Hourly Salary USD 35.00 - 41.00
**Category**: Engineering
**Industry**: Technology

**Apply**: https://hpe.wd5.myworkdayjobs.com/en-US/Jobsathpe/job/Roseville-California-United-States-of-America/ASIC-Verification-Engineering-Intern_1214028?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_bd570c2c-3a4

## Description

Aruba, a Hewlett Packard Enterprise Company, is seeking an ASIC Post-Si Verification Engineering Intern to join our team in Roseville, CA.

The company designs and delivers Mobility-Defined Networks that empower IT departments and #GenMobile, a new generation of tech-savvy users who rely on their mobile devices for every aspect of work and personal communication.

**Responsibilities:** The intern will work with the HPE Aruba ASIC development team on next-generation products and have a summer project contributing to current or future ASIC development activities.

Key responsibilities include:

- Working with senior members of the ASIC/VLSI team

- Contributing to RTL/Physical Design, Pre-Silicon verification, Post-Silicon verification, Formal Verification, Script &/or Tool development

- Assisting with schedule breakdowns and document generation

**Education & Experience:**

- Currently pursuing a Bachelor's or Master's degree in Computer Engineering, Computer Science, Electrical Engineering, or a related technical field

- At least 3rd Year of engineering courses completed

**Knowledge & Skills:**

- Basic programming or scripting knowledge (e.g., Verilog, SystemVerilog, Python, PERL, TCL, C, C++)

- Experience with hardware design

- Strong interest in high-tech and a passion for learning

- Excellent communication and interpersonal skills

- Strong problem-solving and analytical skills

- Ability to work within a team environment

**Benefits:**

- Comprehensive suite of benefits supporting physical, financial, and emotional wellbeing

- Investment in career development with programs to help reach career goals

- Unconditional inclusion with a focus on individual uniqueness and flexibility to manage work and personal needs

**Salary:** Hourly Salary USD 35.00 - 41.00 in California

## Skills

### Required
- Verilog
- SystemVerilog
- Python
- PERL
- TCL
- C
- C++
- hardware design

---

Source: [Apply at hpe.wd5.myworkdayjobs.com](https://hpe.wd5.myworkdayjobs.com/en-US/Jobsathpe/job/Roseville-California-United-States-of-America/ASIC-Verification-Engineering-Intern_1214028?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)