# Senior FPGA Verification Engineer, Air Dominance and Strike

**Company**: Anduril
**Location**: Costa Mesa, California
**Experience**: senior
**Job type**: full-time
**Salary**: $166,000-$220,000 USD
**Category**: Engineering
**Industry**: Technology

**Apply**: https://job-boards.greenhouse.io/andurilindustries/jobs/5228707007?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_bbeae35f-909

## Description

We are looking for a Senior FPGA Verification Engineer to join our rapidly growing team in Costa Mesa, CA.

You will own verification of FPGA/SoC designs on AMD (Xilinx) platforms for flight-critical avionics, with a focus on UVM-based methodology and coverage-driven verification.

**Responsibilities**

- Architect and implement UVM verification environments (drivers, monitors, predictors, scoreboards) for AMD (Xilinx) FPGA/SoC designs

- Develop verification plans with traceability to system and hardware requirements

- Author SystemVerilog Assertions (SVA) for protocol compliance and design intent checks

- Build functional coverage models and drive code coverage analysis to closure

- Develop constrained-random and transaction-level test sequences to maximize coverage and uncover corner-case bugs

- Establish and maintain regression suites, tracking coverage metrics and verification progress

- Debug failures using waveform tools and simulation logs at the HDL and system level

- Collaborate with design engineers on RTL reviews, bug resolution, and micro-architecture refinement

- Support hardware validation and board bring-up on target platforms

- Ensure verification meets DO-254 and relevant safety standards

- Author verification closure reports and coverage analysis summaries

**Required Qualifications**

- Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field

- 8+ years of experience in FPGA/ASIC verification

- Proficient in SystemVerilog, UVM methodology and SVA, with experience contributing to and extending UVM testbenches

- Object-oriented programming principles

- Industry simulators (Questa, VCS, Xcelium, or Vivado)

- Git-based collaborative workflows including code review

- Linux development environments

- Strong communication and teamwork skills

- Eligible to obtain and hold a U.S. Secret security clearance

**Preferred Qualifications**

- 12+ years of experience in FPGA/ASIC verification

- Master’s degree in Electrical Engineering, Computer Engineering, or related field

- DO-254, avionics verification standards for UAS, and safety-critical verification processes

- SVUnit or equivalent unit-testing frameworks

- Formal verification or CDC verification tools

- Digital interfaces: Ethernet, PCIe, JESD204C, MIL-STD-1553, SPI

- Verification automation scripting (Python, Tcl, Makefile)

- SoC and ARM-based embedded platforms

- Verification automation, CI/CD integration, and Nix-based build environments

**Benefits**

Anduril offers a comprehensive, competitive benefits package (available at little to no cost to employees) to support you in health, recovery, and whatever comes next.

## Skills

### Required
- SystemVerilog
- UVM methodology
- SVA
- Object-oriented programming
- Questa
- VCS
- Xcelium
- Vivado
- Git
- Linux

### Nice to have
- DO-254
- avionics verification standards
- SVUnit
- Formal verification
- CDC verification tools
- Ethernet
- PCIe
- JESD204C
- MIL-STD-1553
- SPI
- Python
- Tcl
- Makefile
- SoC
- ARM-based embedded platforms

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Source: [Apply at job-boards.greenhouse.io](https://job-boards.greenhouse.io/andurilindustries/jobs/5228707007?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)