# Staff Applications Engineer

**Company**: Synopsys
**Location**: Sunnyvale, California
**Experience**: staff
**Job type**: full-time
**Salary**: $129000-$193000
**Category**: Engineering
**Industry**: Technology
**Ticker**: SNPS
**Wikidata**: https://www.wikidata.org/wiki/Q2303478

**Apply**: https://careers.synopsys.com/job/sunnyvale/staff-applications-engineer/44408/99760751936?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_bbb86e52-c57

## Description

You will work as a Staff Applications Engineer at Synopsys, leading formal verification deployments with customers, assessing their design environments, verification gaps, and RTL complexity to recommend methodologies that fit their workflow.

Responsibilities:

- Lead formal verification deployments with customers

- Diagnose root causes of formal tool performance issues

- Identify design blocks and verification scenarios for formal property checking, sequential equivalence checking, connectivity checking, or formal coverage analysis

- Develop and deliver technical training on new formal features and product updates

- Work directly with Synopsys R&D and product engineering teams to communicate customer priorities, tool limitations, and feature requests

- Support customers through complex formal runs

- Build reusable formal verification flows and best practices

The Impact You Will Have:

- Enable customers to catch critical design bugs earlier in the verification cycle

- Drive adoption of formal verification across customer organizations

- Influence Synopsys product direction by surfacing real customer pain points and use cases

- Reduce formal runtime bottlenecks and false negatives

- Build customer trust and long-term relationships

- Expand the footprint of Synopsys formal solutions within accounts

What You'll Need:

- Bachelor's or Master's degree in Electrical Engineering or Computer Engineering

- 5-7 years of hands-on experience in RTL design or verification

- Deep understanding of formal verification applications

- Strong grasp of hardware design languages like Verilog or VHDL

- Proficiency in Unix/Linux environments with solid scripting skills

- Experience with assertion-based verification is strongly preferred

Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.

## Skills

### Required
- formal verification
- RTL design
- hardware design languages
- Unix/Linux scripting
- assertion-based verification

### Nice to have
- sequential equivalence checking
- formal coverage analysis
- connectivity checking

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Source: [Apply at careers.synopsys.com](https://careers.synopsys.com/job/sunnyvale/staff-applications-engineer/44408/99760751936?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)