# Senior Signal and Power Integrity Engineer

**Company**: NVIDIA
**Location**: Santa Clara
**Work arrangement**: onsite
**Experience**: senior
**Job type**: full-time
**Category**: Engineering
**Industry**: Technology

**Apply**: https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-Signal-and-Power-Integrity-Engineer_JR2016926?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_baca09a4-111

## Description

We are now looking for a Senior Signal & Power Integrity Engineer!

NVIDIA is a technology company that has been in operation for over two decades, with a focus on developing innovative products and solutions. This position offers the opportunity to have real impact in a multifaceted, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence.

**Responsibilities:**

- Lead board/system SI design activities, PCB stack up design, material selection, design guide implementation, layout review, and post-layout analysis.

- System-level signal integrity simulation of PCIE, LPDDR/DDR/GDDR, MIPI, HDMI, USB and other interfaces.

- Analyze and optimize Power delivery network (PDN) on PCBs.

- Work closely with Package and PCB Design teams crafting solutions for system SI/PI performance.

- Work with Application Engineering supporting customer board designs.

- TDR & VNA measurement for PKG/PCB material characterization and model correlation

**Requirements:**

- BS/MS in Electrical Engineering (or equivalent experience) with minimum 4 years of experience as a SI/PI engineer

- Good understanding of electromagnetics, channel components and transmission line theory

- Experience with design and implementation of one or more high speed electrical interfaces, such as PCIE, LPDDR/DDR/GDDR, MIPI, HDMI, USB etc.

- Hands on experience with HFSS, Sigrity, Hspice or similar industry standard simulation tools

- Experienced with Cadence Allegro PCB designer and Constraints Manager and or other PCB stack up designer tools.

- Understanding of impacts of high-volume PCB manufacturing on channel signal integrity

**Preferred Qualifications:**

- Expertise in one or more of the high-speed interface SI/PI designs on any industry standard system platforms.

- Exposure to package design, interface timing budgets and system modeling

- Familiarity with high-speed transmitter, receiver design and various equalization schemes

- Familiarity with various signaling schemes like NRZ, PAM4 is a plus.

You will also be eligible for equity and benefits.

## Skills

### Required
- Electrical Engineering
- Signal Integrity
- Power Integrity
- PCB Stack Up Design
- Material Selection
- Design Guide Implementation
- Layout Review
- Post-Layout Analysis
- System-Level Signal Integrity Simulation
- PCIE
- LPDDR/DDR/GDDR
- MIPI
- HDMI
- USB
- HFSS
- Sigrity
- Hspice
- Cadence Allegro PCB Designer
- Constraints Manager

### Nice to have
- High-Speed Interface SI/PI Designs
- Package Design
- Interface Timing Budgets
- System Modeling
- High-Speed Transmitter
- Receiver Design
- Equalization Schemes
- NRZ
- PAM4

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Source: [Apply at nvidia.wd5.myworkdayjobs.com](https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-Signal-and-Power-Integrity-Engineer_JR2016926?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)