# ASIC Design Engineer

**Company**: Cisco
**Location**: San Jose, California
**Experience**: senior
**Job type**: full-time
**Salary**: $167,700.00 - $245,200.00
**Category**: Engineering
**Industry**: Technology

**Apply**: https://cisco.wd5.myworkdayjobs.com/en-US/Cisco_Careers/job/San-Jose-California-US/ASIC-Engineer_2028864?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_b8f80286-fe1

## Description

Join Cisco Silicon One, a team of experts designing and building complex high-performance Silicon ASICs. As an ASIC Design Engineer, you will define, design, and take end-to-end ownership of ASIC subsystems to be deployed in a range of Cisco platforms.

Responsibilities:

- Work on challenging problems in high-performance silicon for hyperscale infrastructure.

- Design and implement high-frequency, high-performance RTL in Verilog/SystemVerilog, meeting aggressive timing, power, and area targets.

- Lead design specifications and technical reviews, ensuring architectural clarity and high-quality implementation.

- Drive technical execution across architecture, design, verification, and physical implementation teams to deliver robust silicon.

- Collaborate closely with verification and physical design teams to close functional coverage, timing, and integration challenges.

- Mentor engineers and elevate engineering rigor, design quality, and technical execution across the team.

- Lead debug and root-cause analysis across simulation, system bring-up, and post-silicon validation.

- Create reusable code that promotes efficiencies in new ways.

- Influence system architecture and key design decisions across complex ASIC subsystems.

Minimum Qualifications:

- Bachelor's degree in Electrical or Computer Engineering and 7+ years of ASIC design experience, or Master's degree in Electrical or Computer Engineering and 4+ years of ASIC design experience.

- ASIC design experience, delivering silicon from microarchitecture, specification, and RTL coding through tape-out with multiple ASIC tape-outs at advanced technology nodes.

- Experience in high-performance RTL design using Verilog/SystemVerilog.

- Understanding of timing closure, power optimization, and clock gating techniques.

- Experience with ASIC development flows including simulation, synthesis, and static timing analysis.

Benefits:

- Medical, dental, and vision insurance

- 401(k) plan with Cisco matching contribution

- Paid parental leave

- Short and long-term disability coverage

- Basic life insurance

- Paid time away (vacation, holidays, sick time)

- Opportunities for career growth and professional development

Salary Range: $167,700.00 - $245,200.00 per year

## Skills

### Required
- ASIC design
- Verilog
- SystemVerilog
- RTL design
- timing closure
- power optimization

### Nice to have
- documentation
- problem-solving
- technical communication
- cross-functional collaboration

---

Source: [Apply at cisco.wd5.myworkdayjobs.com](https://cisco.wd5.myworkdayjobs.com/en-US/Cisco_Careers/job/San-Jose-California-US/ASIC-Engineer_2028864?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)