# Digital Design, Senior Engineer

**Company**: Synopsys
**Location**: Bengaluru, Karnataka
**Experience**: senior
**Job type**: employee
**Category**: Engineering
**Industry**: Technology
**Ticker**: SNPS
**Wikidata**: https://www.wikidata.org/wiki/Q2303478

**Apply**: https://careers.synopsys.com/job/bengaluru/digital-design-senior-engineer/44408/101087862608?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_b8cad302-502

## Description

Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.

As a Senior ASIC Digital Design Engineer, you will deliver high-quality RTL for complex PCIe IP. You will take a spec or micro-architecture, implement it cleanly, debug it thoroughly, and stand behind the block you own.

Responsibilities:

- Implement and own RTL for PCIe blocks and features from micro-architecture and design specs.

- Debug design issues in simulation and, as needed, in formal, emulation, or silicon bring-up support.

- Contribute to micro-architecture discussions for your blocks; document design intent and corner cases.

- Follow and help enforce RTL coding standards, lint/CDC hygiene, and review comments to closure.

- Work with verification to define coverage intent, root-cause failures, and deliver fixes on schedule.

- Support synthesis, timing, and low-power feedback from physical design for your blocks.

- Develop toward broader subsystem ownership with mentoring from Staff and Principal engineers.

Requirements:

- BSEE with 5+ years of relevant experience, or MSEE with 3+ years (or equivalent).

- Hands-on ASIC RTL design in SystemVerilog on production designs.

- Experience with at least one of: PCIe, CXL, AMBA/AXI, DDR, Ethernet, or other high-speed / on-chip interconnect data paths.

- Working knowledge of clocking, resets, FSMs, pipelines, and synthesizable design practice.

- Familiarity with simulation debug; lint, CDC, or synthesis exposure is a plus.

- Scripting (Python, TCL, Perl) and AI-assisted design tools are a plus.

Benefits:

- Comprehensive medical and healthcare plans that work for you and your family.

- In addition to company holidays, we have ETO and FTO Programs.

- Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.

- Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.

- Save for your future with our retirement plans that vary by region and country.

- Competitive salaries.

## Skills

### Required
- ASIC RTL design
- SystemVerilog
- PCIe
- CXL
- AMBA/AXI
- DDR
- Ethernet
- clocking
- resets
- FSMs
- pipelines
- synthesizable design practice
- simulation debug
- lint
- CDC
- synthesis
- Python
- TCL
- Perl

### Nice to have
- high-speed interfaces
- data-path experience
- AI-assisted design tools

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Source: [Apply at careers.synopsys.com](https://careers.synopsys.com/job/bengaluru/digital-design-senior-engineer/44408/101087862608?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)