# Senior DFT Methodology Engineer

**Company**: NVIDIA
**Experience**: senior
**Job type**: full-time
**Salary**: $168,000 - $264,500 (Level 4) or $196,000 - $310,500 (Level 5)
**Category**: Engineering
**Industry**: Technology

**Apply**: https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-DFT-Methodology-Engineer_JR2026996-1?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_b70adbb1-047

## Description

We are seeking a Senior DFT Methodology Engineer to architect and develop test methodologies for our next-generation silicon products. As a Senior DFT Methodology Engineer, you will work on implementing state-of-the-art designs in test access mechanisms, I1149.1, I1500, I1687, 1838, memory BIST, memory dump, and DFX security methodology.

You will partner closely with cross-functional teams, including timing, physical design, software, bring-up, and production teams to make the right trade-offs between cost and quality. Additionally, you will help architect, develop, and deploy DFT methodologies for our next-generation products, including RTL design, verification, pattern generation, and partnering with teams like timing, physical design, software, bring-up, and production.

You will also mentor junior engineers on test designs and trade-offs, including cost and quality.

**Requirements:**

- BS/MS Electrical or Computer Engineering (or equivalent experience) in a related domain with proven DFT experience

- 10+ years of hands-on experience in SoC architecture, RTL design, and verification

- Strong analytical skills, with experience using vendor tools to verify and validate test patterns and logic on highly complex, multi-million-gate designs

- Good exposure to cross-functional areas, including RTL & clocks design, STA, place-n-route, and power

- Experience in silicon debug and bring-up on the ATE with an understanding of pattern formats, failure processing, and test program development

- Exceptional written and oral interpersonal skills with the curiosity to work on rare challenges

**Preferred Qualifications:**

- Knowledge of DFT security and hardware system security is a plus

- Strong programming and scripting skills in Perl, Python, or Tcl

- Proven track record of successfully deploying advanced DFT methodologies in groundbreaking semiconductor technologies

- Experience mentoring engineers and driving methodology adoption across multiple product generations

- Strong problem-solving skills and a proactive approach to overcoming technical challenges

**What We Offer:**

- Competitive compensation: $168,000 - $264,500 (Level 4) or $196,000 - $310,500 (Level 5)

- Comprehensive benefits

- Meaningful opportunities to advance your career

## Skills

### Required
- DFT
- SoC architecture
- RTL design
- verification
- analytical skills
- interpersonal skills

### Nice to have
- DFT security
- hardware system security
- Perl
- Python
- Tcl
- scripting skills
- problem-solving skills

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Source: [Apply at nvidia.wd5.myworkdayjobs.com](https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-DFT-Methodology-Engineer_JR2026996-1?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)