# R&D Engineering, Staff Engineer

**Company**: Synopsys
**Location**: Bhubaneswar, Odisha
**Work arrangement**: onsite
**Experience**: staff
**Job type**: full-time
**Category**: Engineering
**Industry**: Technology
**Ticker**: SNPS
**Wikidata**: https://www.wikidata.org/wiki/Q2303478

**Apply**: https://careers.synopsys.com/job/bhubaneswar/r-and-d-engineering-staff-engineer/44408/95947919888?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_b44fb0d4-d2c

## Description

You will work on SoC designs that power real products, alongside engineers who care as much about the details as you do.

Design and develop RTL using Verilog and SystemVerilog for complex SoC and ASIC components that go into production silicon.

Integrate IP blocks at the SoC level, building the glue logic and subsystem architecture that makes everything actually work together.

Write SDC for synthesis, ensuring your constraints reflect the real timing intent and do not create downstream surprises.

Run and debug lint, CDC, and synthesis checks using tools like SpyGlass, Fusion Compiler, and Encounter, resolving issues before they become integration blockers.

Collaborate with verification, physical design, and architecture teams to close functional and structural issues across the design cycle.

Contribute to microarchitecture discussions and translate architectural intent into working RTL that meets performance, power, and area targets.

Mentor junior engineers on RTL quality, coding standards, and front-end design best practices when the opportunity arises.

Your RTL integration work directly enables complex SoCs to move from architecture to physical implementation without costly respins.

The synthesis constraints you write determine whether the design meets timing on the first pass or requires weeks of iteration.

Your ability to debug CDC and lint issues early prevents verification and physical design teams from hitting walls later in the schedule.

The glue logic and subsystem designs you build become the connective tissue that makes multi-IP integration actually function.

Your technical guidance helps junior engineers avoid common pitfalls and build higher-quality RTL from the start.

The blocks you own and deliver on schedule keep entire project timelines on track.

Your collaboration across teams ensures that architectural intent, RTL implementation, and physical constraints stay aligned throughout the design cycle.

## Skills

### Required
- RTL design
- SoC integration
- Verilog
- SystemVerilog
- SDC
- lint tools
- CDC analysis tools
- synthesis flows

### Nice to have
- AI tools
- high-speed interfaces
- low-power design techniques
- scripting in Python, Tcl, or Perl

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Source: [Apply at careers.synopsys.com](https://careers.synopsys.com/job/bhubaneswar/r-and-d-engineering-staff-engineer/44408/95947919888?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)