# Senior ASIC Design Engineer

**Company**: NVIDIA
**Location**: Santa Clara
**Work arrangement**: onsite
**Experience**: senior
**Job type**: full-time
**Category**: Engineering
**Industry**: Technology

**Apply**: https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-ASIC-Design-Engineer_JR2014978?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_b11255b6-792

## Description

As a Senior ASIC Design Engineer at NVIDIA, you will be essential in documenting, implementing, and delivering fully verified, high-performance, area- and power-efficient RTL to meet design goals and specifications.

Your daily duties will include: Crafting architecture and micro-architecture, as well as conducting RTL design and synthesis. Performing logic and timing verification using advanced CAD tools and semiconductor process technologies. Participating in the verification of builds through sophisticated methodologies, including the development of design properties and assumptions for formal verification. Collaborating closely with several ASIC development teams, ensuring seamless communication and coordination to successfully implement build requirements.

A Bachelor's or equivalent experience, or a Master's degree or equivalent experience in a relevant field, with 5+ years of experience is required.

You will also be eligible for equity and benefits.

## Skills

### Required
- Verilog
- System Verilog
- Perl/Python
- C/C++
- Logic synthesis
- Timing analysis
- High-speed energy-efficient data paths
- Build and verification tools
- Simulation tools
- Debug tools
- Test bench environments
- Unit and system-level verification
- Random stimulus
- Functional coverage
- Assertion-based verification methodologies

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Source: [Apply at nvidia.wd5.myworkdayjobs.com](https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-ASIC-Design-Engineer_JR2014978?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)