# ASIC DFT Emulation Technical Lead

**Company**: Cisco
**Location**: San Jose, California
**Work arrangement**: onsite
**Experience**: senior
**Job type**: full-time
**Salary**: $186,900.00 to $267,700.00
**Category**: Engineering
**Industry**: Technology

**Apply**: https://cisco.wd5.myworkdayjobs.com/en-US/Cisco_Careers/job/San-Jose-California-US/ASIC-DFT-Emulation-Technical-Lead_2019597?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_b0b5c153-088

## Description

The Common Hardware Group at Cisco delivers silicon, optics, and hardware platforms for core Switching, Routing, and Wireless products.

As an ASIC DFT - Emulation Technical Lead, you will play a critical role in driving the DFT emulation strategy for Silicon One.

You'll architect state-of-the-art emulation environments, lead pre-silicon test plan execution, and validate complex scan, MBIST, and JTAG architectures on platforms like Palladium, Veloce, or Zebu.

Partnering closely with front-end RTL, physical design, and ATPG teams, you will troubleshoot critical issues and ensure high-quality post-silicon pattern conversion.

Your technical leadership and cross-functional collaboration will guarantee seamless silicon bring-up and optimal test coverage across next-generation hardware platforms.

**Minimum Qualifications**

- Bachelor's + 8 years of related experience, or Master's + 6 years of related experience, or PhD + 3 years of related experience

- Prior emulation experience on platforms such as Palladium, Veloce, or Zebu as well as experience with compilation and debug.

- Prior experience with Verilog and System Verilog.

- Prior experience with C/C++ and scripting skills with Tcl or Python/Perl.

**Preferred Qualifications**

- Prior experience defining DFT Emulation strategy.

- Prior experience with JTAG protocol, scan architecture, MBIST and boundary scan.

- UVM and advanced System Verilog knowledge.

- Post Silicon validation and/or debugging experience.

The starting salary range posted for this position is $186,900.00 to $267,700.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.

U.S. employees are offered benefits, subject to Cisco’s plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance.

## Skills

### Required
- Verilog
- System Verilog
- C/C++
- Tcl
- Python/Perl
- Palladium
- Veloce
- Zebu

### Nice to have
- JTAG protocol
- scan architecture
- MBIST
- boundary scan
- UVM
- advanced System Verilog
- Post Silicon validation
- debugging

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