# Silicon One Development Engineer

**Company**: Cisco
**Location**: San Jose, California
**Experience**: senior
**Job type**: full-time
**Salary**: $167,700.00 - $245,200.00
**Category**: Engineering
**Industry**: Technology

**Apply**: https://cisco.wd5.myworkdayjobs.com/en-US/Cisco_Careers/job/San-Jose-California-US/Senior-ASIC-RTL-Engineer_2028011?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_b08d724c-df5

## Description

The Silicon One team at Cisco creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally.

You will be a key member of the Silicon One development organization, collaborating closely with Front-end RTL and backend physical design teams to gain a deep understanding of chip architecture. Your primary focus will be to drive high-quality Design for Test (DFT) RTL, ensuring robust and reliable silicon solutions that meet Cisco’s standards for performance and innovation.

**Minimum Qualifications:**

- Bachelor's or a Master's Degree in Electrical or Computer Engineering required with at least 8 years of experience

- Prior experience in Verilog/System Verilog coding

- Prior experience with front-end tools (Verilog simulators, linting, CDC checkers, synthesis, formal verification)

- Prior experience with industry standard interface protocols such as AMBA(AXI, APB, AHB), JTAG etc, memories

**Preferred Qualifications:**

- Prior experience with power optimization techniques, power intent (UPF), power estimation

- Prior experience with DFT/MBIST is a plus

- Prior experience with post-silicon debug

**Benefits:**

- Medical, dental and vision insurance

- 401(k) plan with a Cisco matching contribution

- Paid parental leave

- Short and long-term disability coverage

- Basic life insurance

- 10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees

- 1 paid day off for employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness

- Non-exempt employees receive 16 days of paid vacation time per full calendar year

- Exempt employees participate in Cisco’s flexible vacation time off program

- 80 hours of sick time off provided on hire date and each January 1st thereafter

- Optional 10 paid days per full calendar year to volunteer

**Salary Range:** $167,700.00 - $245,200.00

## Skills

### Required
- Verilog
- System Verilog
- front-end tools
- AMBA
- JTAG

### Nice to have
- power optimization techniques
- DFT/MBIST
- post-silicon debug

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Source: [Apply at cisco.wd5.myworkdayjobs.com](https://cisco.wd5.myworkdayjobs.com/en-US/Cisco_Careers/job/San-Jose-California-US/Senior-ASIC-RTL-Engineer_2028011?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)