# ASIC Digital Design Engineer

**Company**: Cisco
**Location**: Yerevan
**Work arrangement**: hybrid
**Experience**: senior
**Job type**: full-time
**Category**: Engineering
**Industry**: Technology

**Apply**: https://cisco.wd5.myworkdayjobs.com/en-US/Cisco_Careers/job/Armenia/ASIC-Engineering-Technical-Leader_2006866?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_afe21506-aee

## Description

This is a hybrid role with four days per week at Cisco’s Yerevan office.

Join the Silicon One Team at Cisco in Armenia, a group at the forefront of developing Cisco's groundbreaking silicon architecture. We are a collaborative unit focused on pushing the boundaries of ASIC design for advanced process nodes. As part of our team, you will contribute to defining innovative Physical Design methodologies and creating robust flows essential for developing our complex chips. You will also have the opportunity to work firsthand with the Physical Design of intricate chip partitions.

As a key technical leader, you will drive next-generation silicon architecture development, guide your team in delivering solutions that power advanced global networks, and lead collaboration across multiple teams. You will mentor engineers and influence physical design strategies that set new industry standards. Your expertise will be critical to the successful delivery and continuous improvement of Cisco’s most advanced silicon solutions.

Responsibilities:

- Taking part in all aspects of digital design, from micro-architecture to RTL design and qualification.

- Sub-system/SoC integration and verification.

- Review/enhancement of RTL codes.

- Improve flows and methodologies to streamline IP/SoC development and integration.

- Work closely with the verification team for complex debugs to resolve verification failures.

- Close interaction with the physical design team to reach better physical design QoR.

Minimum Qualifications:

- 8+ years of industry experience in ASIC digital design.

- Proficient in Verilog/System Verilog coding.

- Experience with front-end tools (Verilog simulators, linting, CDC checkers, synthesis, formal verification).

- Experience with industry standard interface protocols such as AMBA(AXI, APB, AHB), JTAG etc, memories.

- Ability to write scripts using Python, Tcl, Make.

Preferred Qualifications:

- Experience working on sensors IP development.

- Familiarity with power optimization techniques, power intent (UPF), power estimation.

- Familiarity with DFT/MBIST is a plus.

- Good communication skills, self-motivated and well-organized.

## Skills

### Required
- ASIC digital design
- Verilog
- System Verilog
- Python
- Tcl
- Make
- AMBA
- JTAG

### Nice to have
- sensors IP development
- power optimization techniques
- DFT/MBIST

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Source: [Apply at cisco.wd5.myworkdayjobs.com](https://cisco.wd5.myworkdayjobs.com/en-US/Cisco_Careers/job/Armenia/ASIC-Engineering-Technical-Leader_2006866?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)