# EDA flow and Logic Synthesis Engineer (Staff Engineer) **Company**: Synopsys **Location**: Dublin, Leinster **Experience**: staff **Job type**: employee **Category**: Engineering **Industry**: Technology **Ticker**: SNPS **Wikidata**: https://www.wikidata.org/wiki/Q2303478 **Apply**: https://careers.synopsys.com/job/dublin/eda-flow-and-logic-synthesis-engineer-staff-engineer/44408/97142011088?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply **Canonical**: https://yubhub.co/jobs/job_af8ddc9d-7c3 ## Description Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. Within our HPC Controller IP organization, the mid-end team is the bridge between RTL design and physical implementation. We build the flows, automation, and quality checks that synthesize, verify, package, and release complex soft IP at scale , and we hand physical-design teams inputs that are clean, constrained, and implementation-ready. You are a motivated mid-end engineer with a solid grasp of ASIC design and verification flows, and genuine enthusiasm for automation, flow robustness, and using AI to raise engineering productivity, debug speed, and quality of results. You partner naturally with RTL designers to understand design intent, turn their outputs into physical-design-ready inputs, and collaborate across verification, DFT, physical design, methodology, and tooling teams. You communicate clearly, take ownership, and let data guide your decisions. **Responsibilities** - Develop, run, and support mid-end flows spanning synthesis, DFT, static checking (SpyGlass), formal equivalence, power analysis, and related quality gates. - Convert RTL outputs into clean, constrained, implementation-ready inputs for physical design. - Build and maintain Tcl-based automation, dashboards, and project infrastructure , and apply AI to accelerate the work (e.g., triaging flow logs, summarizing QoR trends, drafting and refactoring scripts). - Debug flow failures end to end: analyze reports, isolate root cause, and drive issues to closure with design, verification, DFT, and implementation teams. - Improve documentation, handoff criteria, and reusable collateral so execution stays consistent across IP programs. **The Impact You Will Have** - Higher-quality RTL-to-physical-design handoffs and lower implementation risk. - Faster, more scalable execution through stronger automation and AI-enabled analysis. - Synthesis, DFT, static, formal, and power issues caught earlier in the cycle. - Tighter collaboration across the RTL-to-implementation chain. - Robust, implementation-ready soft IP shipped with clear constraints, checks, and release collateral. **Requirements** - Working knowledge of ASIC design, verification, and mid-end development flows, typically gained through 5+ years of relevant experience or equivalent project work. - Hands-on synthesis experience, with the ability to analyze and resolve synthesis issues. - Strong Tcl scripting skills and a practical, automation-first mindset. - Familiarity with at least two of: DFT concepts, static checking (SpyGlass or equivalent), formal equivalence (e.g., Formality), or power analysis , and willingness to grow across the rest. - Ability to use AI tools effectively to accelerate debugging, summarize results, and improve scripts and flows. - Strong analytical, problem-solving, communication, and documentation skills. - BS/MS in Electrical/Computer Engineering or equivalent experience. **Benefits** - Comprehensive medical and healthcare plans that work for you and your family. - In addition to company holidays, we have ETO and FTO Programs. - Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more. - Purchase Synopsys common stock at a 15% discount, with a 24-month look-back. - Save for your future with our retirement plans that vary by region and country. - Competitive salaries. ## Skills ### Required - ASIC design - verification flows - synthesis - DFT - static checking - formal equivalence - power analysis - Tcl scripting - AI tools ### Nice to have - IP development methodologies - IP packaging - reusable IP delivery - Synopsys tools such as Fusion Compiler and VCSpyGlass --- Source: [Apply at careers.synopsys.com](https://careers.synopsys.com/job/dublin/eda-flow-and-logic-synthesis-engineer-staff-engineer/44408/97142011088?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)