# Architect - Subsystem Interoperability & AI-Driven Verification **Company**: Synopsys **Location**: Bengaluru, Karnataka **Work arrangement**: onsite **Experience**: senior **Job type**: full-time **Category**: Engineering **Industry**: Technology **Ticker**: SNPS **Wikidata**: https://www.wikidata.org/wiki/Q2303478 **Apply**: https://careers.synopsys.com/job/bengaluru/architect-subsystem-interoperability-and-ai-driven-verification/44408/103259314880?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply **Canonical**: https://yubhub.co/job/architect-subsystem-interoperability-and-ai-driven-ada0e267-726/ ## Description You are a recognized technical leader who thinks in systems, not individual IP blocks. You understand where interoperability challenges emerge at architectural boundaries, configurations, initialization sequences, protocol interactions, firmware dependencies, clock and reset domains, implementation constraints and assumptions made between independently developed IP. **What You'll Be Doing** - Define the technical vision for subsystem interoperability spanning Controller, PHY, firmware, VIP, verification environments, and customer configurations across multiple high-speed interface IP families - Architect a scalable Interop Verification Platform that enables continuous integration, verification, and qualification across IP releases, solving the configuration challenge across Controller × PHY × Firmware × VIP × Protocol Mode × Customer Configuration using intelligent risk and coverage-based qualification - Establish reusable verification architectures, methodologies and golden reference environments covering functional verification, protocol compliance, error and stress scenarios, coverage, assertions, CDC/RDC and system initialization - Lead the most complex cross-IP technical investigations and drive systemic solutions across RTL, PHY, firmware, VIP, testbench and implementation boundaries when interoperability issues surface - Partner with Controller and PHY architects and R&D teams to influence interfaces, observability, design-for-verification and subsystem architecture early in the development lifecycle - Pioneer an AI-native verification architecture that applies GenAI, LLMs, RAG and agentic workflows across the verification lifecycle: specification to verification intent to environment to tests to regression to debug to qualification to learning - Architect AI-assisted generation of environments and tests, intelligent regression selection, automated log and failure clustering, coverage-gap analysis, protocol and waveform debug, root-cause recommendations, engineering knowledge retrieval and automated qualification evidence **The Impact You Will Have** - Transform interoperability from a late-stage integration activity into a continuous product capability that accelerates subsystem bring-up and qualification across Synopsys IP portfolios - Scale verification across increasingly complex IP configurations, enabling Synopsys to deliver subsystems that work together seamlessly before they reach customer environments - Convert field issues into permanent prevention tests and reusable engineering knowledge, reducing repeat failures and building institutional memory into the verification platform - Establish common interoperability methodology across multiple IP families including UCIe, PCIe/CXL, Ethernet, DDR/HBM, USB and AMBA/CHI, creating consistency and reuse across product lines - Create an AI-native verification architecture capable of scaling engineering expertise across products and organizations, fundamentally changing how Synopsys qualifies complex subsystems - Define compatibility matrices and qualification criteria that provide clear, evidence-based confidence that a specific Controller-PHY combination is customer ready, reducing integration risk and time-to-market - Mentor senior engineers and serve as a technical authority for subsystem interoperability, raising the bar for verification excellence across the organization **What You'll Need** - 15+ years of ASIC/IP/SoC verification experience with demonstrated technical leadership on complex verification programs where you defined architecture, influenced direction, and delivered results across organizational boundaries - Deep expertise in SystemVerilog, UVM, assertions, functional and code coverage, verification closure and complex debug, with hands-on experience building and reviewing sophisticated verification environments - Proven experience architecting reusable verification environments for IP, subsystem or SoC designs that scaled across multiple projects or product lines - Strong expertise in one or more high-speed protocols such as UCIe, PCIe/CXL, Ethernet, DDR/HBM, USB or AMBA/CHI, with deep understanding of protocol interactions, initialization sequences, and interoperability challenges - Hands-on expertise with industry-standard simulation and debug tools, VIP and coverage infrastructure, specifically VCS and Verdi or equivalent toolchains - Strong automation expertise in Python, Tcl or equivalent scripting languages, with a track record of building tools that improve verification productivity - Experience with CDC/RDC, formal verification, emulation/prototyping, CI/CD or distributed verification infrastructure is highly desirable, as is experience or strong interest in GenAI, LLMs, RAG, agentic AI and AI-assisted verification For more fresh new jobs, check out [yubhub.co](https://yubhub.co/). ## Skills ### Required - SystemVerilog - UVM - Python - PCIe - Ethernet - DDR/HBM - USB - AMBA/CHI - GenAI - LLMs ### Nice to have - CDC/RDC - formal verification - emulation/prototyping - CI/CD - distributed verification infrastructure --- Source: [Apply at careers.synopsys.com](https://careers.synopsys.com/job/bengaluru/architect-subsystem-interoperability-and-ai-driven-verification/44408/103259314880?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)