# ASIC Engineering Digital Design Leader (Digital design, FSM, CPU sub-systems, complex SOCs)

**Company**: Cisco
**Location**: Pune
**Work arrangement**: onsite
**Experience**: senior
**Job type**: full-time
**Category**: Engineering
**Industry**: Technology

**Apply**: https://cisco.wd5.myworkdayjobs.com/en-US/Cisco_Careers/job/Pune-India/ASIC-Engineering-Digital-Design-Leader---digital-design--FSM--CPU-sub-systems--complex-SOCs--FPGA-validation---12-16-Years---Pune-_2013153-1?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_ad150590-c67

## Description

Cisco’s Client Optics Group (COG) designs and delivers high-speed optical transceivers and platforms that power Cisco's core data center networking solutions.

You will work with Cisco's outstanding Silicon Photonics team, responsible for driving the development and optimization of optical transceivers and modules that seamlessly integrate with Cisco's routing, switching, and datacenter platforms.

The Digital Design Lead for the Client Optics Group (COG) provides essential technical leadership in the development of digital logic for silicon photonics, ensuring high-performance outcomes for 100G, 200G, and 400G optical interconnects.

Responsibilities include:

- Leading design activities from Pre-Silicon RTL to GDS2 signoff and Post-Silicon activities

- Leading architecture and design of complex digital blocks and CPU subsystems

- Understanding and supporting FW architecture and FW-based verification

- Developing top and block level specifications for high-speed datapath and low-speed control planes

- Reviewing verification coverage and signing off on coverage metrics

- Supporting backend activities such as synthesis, timing closure, DFT, and low-power design

Minimum qualifications:

- Bachelor’s or master’s degree in electrical engineering, Electronics Engineering, or a related field

- 12-16 years of industry experience with hands-on experience in digital design, including FSM and CPU sub-systems, complex SOCs, and FPGA validation

- Strong technical leadership experience of at least 6 years

- Familiarity with protocols such as SPI, I2C, APB, AXI, or similar interfaces and high-speed SerDes, Ethernet, D2D PHY IP, and protocols

- Strong knowledge of ASIC/SoC design flow, including RTL development using SystemVerilog, simulation, lint, CDC/RDC, synthesis, formal/equivalence checking, DFT, and implementation handoff

## Skills

### Required
- digital design
- FSM
- CPU sub-systems
- complex SOCs
- FPGA validation
- ASIC/SoC design flow
- SystemVerilog
- SerDes
- Ethernet
- D2D PHY IP

### Nice to have
- technical leadership
- FW architecture
- verification
- DFT
- low-power design

---

Source: [Apply at cisco.wd5.myworkdayjobs.com](https://cisco.wd5.myworkdayjobs.com/en-US/Cisco_Careers/job/Pune-India/ASIC-Engineering-Digital-Design-Leader---digital-design--FSM--CPU-sub-systems--complex-SOCs--FPGA-validation---12-16-Years---Pune-_2013153-1?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)