# Full-Chip RTL Integration Engineer

**Company**: NVIDIA
**Experience**: senior
**Job type**: full-time
**Salary**: 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5
**Category**: Engineering
**Industry**: Technology

**Apply**: https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-Full-Chip-RTL-Integration-Engineer_JR2027454?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_acae2040-597

## Description

Join NVIDIA's Advanced Technology Group as a Full-Chip RTL Integration Engineer. You will be responsible for integrating complex IPs and subsystems into large-scale SoCs while ensuring design quality, verification readiness, and DFT compliance.

You will work closely with Architecture, Design, Verification, DFT, and Physical Design teams to deliver high-quality silicon products in a collaborative and fast-paced environment.

**Responsibilities:**

- Lead RTL integration of multiple internal and third-party IPs into complex ASIC/SoC designs

- Work closely with Architecture, RTL Design, Verification, DFT, and Physical Design teams to drive system-level integration and design closure

- Perform RTL quality checks including lint, CDC, RDC, synthesis, and connectivity validation

- Develop and carry out integration-level verification plans using SystemVerilog/UVM

- Collaborate with DFT teams to integrate scan, MBIST, LBIST, JTAG, and other test structures

- Support design signoff activities and ensure smooth handoff across implementation stages

- Develop automation and scripting solutions to improve integration, verification, and debug productivity

**Requirements:**

- B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field with 8+ years of experience

- Strong experience in ASIC/SoC RTL Integration

- Excellent understanding of digital design fundamentals, SoC architecture, clocking, reset, and bus protocols

- Strong verification knowledge with hands-on experience in SystemVerilog and UVM

- Ability to independently verify block-level and integration-level designs

- Strong understanding of DFT methodologies including Scan, ATPG, MBIST, LBIST, JTAG, and test compression techniques

- Experience with lint, CDC, RDC, and design quality signoff flows

- Strong debugging, analytical, and problem-solving skills

- Good communication skills and ability to work effectively across multiple engineering teams

**Nice to Have:**

- Experience with large-scale SoC or full-chip integration

- Exposure to Synopsys, Cadence, or Siemens DFT and verification tools

- Experience with low-power design methodologies and UPF

- Proficiency in Python, Perl, Tcl, or Shell scripting

- Ability to bridge integration, verification, and DFT domains to solve complex system-level challenges

NVIDIA offers highly competitive salaries and a comprehensive benefits package.

## Skills

### Required
- ASIC/SoC RTL Integration
- SystemVerilog
- UVM
- DFT methodologies
- Scan
- ATPG
- MBIST
- LBIST
- JTAG
- test compression techniques
- lint
- CDC
- RDC
- design quality signoff flows

### Nice to have
- large-scale SoC or full-chip integration
- Synopsys
- Cadence
- Siemens DFT and verification tools
- low-power design methodologies
- UPF
- Python
- Perl
- Tcl
- Shell scripting

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Source: [Apply at nvidia.wd5.myworkdayjobs.com](https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-Full-Chip-RTL-Integration-Engineer_JR2027454?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)