# Senior ASIC Design Engineer

**Company**: NVIDIA
**Location**: Santa Clara, CA
**Experience**: senior
**Job type**: full-time
**Category**: Engineering
**Industry**: Technology

**Apply**: https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-ASIC-Design-Engineer_JR2009401?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_ab33718a-df0

## Description

NVIDIA is seeking a Senior ASIC Design Engineer to join their team in designing and implementing leading SoCs and GPUs. The successful candidate will have a significant impact on product lines ranging from consumer graphics to self-driving cars and artificial intelligence.

**Job Summary:** As a key member of the Design team, you will be responsible for the implementation of GPU sub-system modules. You will make architectural trade-offs based on features, performance requirements, and system limitations. You are expected to own micro-architecture, implement RTL, and deliver a fully verified, synthesis/timing clean design. You will also support post-silicon validation activities and collaborate with architects, other designers, pre- and post-silicon verification teams, synthesis, timing, and back-end teams.

**Responsibilities:**

- Implement GPU sub-system modules

- Make architectural trade-offs based on features, performance requirements, and system limitations

- Own micro-architecture, implement RTL, and deliver a fully verified, synthesis/timing clean design

- Support post-silicon validation activities

- Collaborate with architects, other designers, pre- and post-silicon verification teams, synthesis, timing, and back-end teams

**Requirements:**

- Master's degree in Electrical Engineering or Computer Engineering

- 8+ years of proven experience working on ASIC design and development

- Experience in micro-architecture and RTL development of complex designs in Verilog

- Exposure to Digital systems and VLSI design, Computer Architecture, Computer Arithmetic, CMOS transistors, and circuits

- Understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up, and lab debug

**Nice to Have:**

- Knowledge of PCI-Express (Gen 3 and above) or CXL protocol

- Experience with Python, Perl, and C/C++ programming languages

- Good debugging and analytical skills

- Strong interpersonal skills and ability to work as a great teammate

**Benefits:**

- Equity

- Benefits package

## Skills

### Required
- ASIC design
- Verilog
- RTL development
- Digital systems
- VLSI design
- Computer Architecture
- Computer Arithmetic
- CMOS transistors
- circuits
- ASIC design flow

### Nice to have
- PCI-Express
- CXL protocol
- Python
- Perl
- C/C++

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Source: [Apply at nvidia.wd5.myworkdayjobs.com](https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-ASIC-Design-Engineer_JR2009401?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)