# Physical Design Staff Application Engineer **Company**: Synopsys **Location**: Hillsboro, Oregon **Experience**: staff **Job type**: full-time **Salary**: $112000-$168000 **Category**: Engineering **Industry**: Technology **Ticker**: SNPS **Wikidata**: https://www.wikidata.org/wiki/Q2303478 **Apply**: https://careers.synopsys.com/job/hillsboro/physical-design-staff-application-engineer/44408/101580799888?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply **Canonical**: https://yubhub.co/jobs/job_a9e79350-5d4 ## Description We are seeking an experienced Physical Design Staff Application Engineer to join our team at Synopsys. As a leader in engineering solutions, we enable customers to rapidly innovate AI-powered products. You will work on the hardest physical design problems in the industry, on the most advanced nodes, with customers who are building the chips that power everything. **Responsibilities** - Support customer engagements on advanced-node designs at 7nm, 5nm, and below using Synopsys physical design tools including Fusion Compiler, helping them hit PPA targets under real schedule and resource constraints - Develop and enhance physical design methodologies and automation solutions using TCL, Python, and Perl to improve design quality, predictability, and team efficiency across the RTL-to-GDS flow - Debug complex physical design challenges including placement, clock tree synthesis, routing, timing closure, and power optimization on FinFET designs with multi-patterning and electromigration constraints - Build and deliver methodology recommendations tailored to customer design constraints, process technologies, and project timelines, not generic best practices but solutions that fit their specific context - Contribute to AI-assisted and machine learning-driven design optimization initiatives, applying data-driven approaches to solve implementation challenges that traditional methods struggle with - Collaborate with R&D, product management, and field teams to translate customer pain points into product requirements and feature enhancements that make it into the next release - Travel to customer sites as needed to provide onsite support, training, and design reviews, often under tight deadlines and high-stakes tape-out pressure **The Impact You Will Have** - Enable customers to achieve timing closure and tape-out success on advanced-node designs that define next-generation AI, mobile, and datacenter products - Build automation and methodology improvements that get reused across multiple customer engagements, multiplying your impact across dozens of designs - Shape the roadmap of Synopsys physical design tools by feeding real customer challenges directly into R&D, influencing features that thousands of engineers will use - Reduce design cycle time and improve PPA outcomes for customers working at the cutting edge of semiconductor technology, where every percentage point of performance or power matters - Mentor field teams and customers on advanced physical design techniques, raising the bar for how complex designs get implemented across the industry - Help drive adoption of AI-driven optimization methodologies that change how physical design gets done, not just incrementally but fundamentally - Strengthen customer relationships by being the engineer they call when a design is stuck and they need someone who can actually solve the problem, not just escalate it **Requirements** - Bachelor's degree in electrical engineering or a related field with 5+ years of hands-on ASIC physical design experience, or a master's degree with 3+ years of experience - Proficiency with industry-standard implementation tools such as Synopsys ICC2, Fusion Compiler, or Cadence Innovus, you have used these tools on real tapeouts, not just in training - Strong scripting and automation skills using TCL, Python, or Perl to build flows, analyze data, and solve problems that do not have a button in the GUI - Solid understanding of advanced-node design challenges at 7nm and below, including FinFET effects, multi-patterning, electromigration, and the tradeoffs that come with each - Experience with logical and physical synthesis flows, and familiarity with AI-driven optimization methodologies is a strong plus - Excellent communication and presentation skills, you can explain a complex timing closure strategy to a customer engineering team and a high-level roadblock to their management in the same meeting - Willingness to travel to customer sites as needed, sometimes on short notice, to provide onsite support during critical design phases ## Skills ### Required - physical design - ASIC design - Fusion Compiler - TCL - Python - Perl - AI-driven optimization ### Nice to have - Cadence Innovus - logical and physical synthesis flows --- Source: [Apply at careers.synopsys.com](https://careers.synopsys.com/job/hillsboro/physical-design-staff-application-engineer/44408/101580799888?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)