# ASIC Digital Verification Engineer: Ethernet / UFS / UniPro / USB (IP Verification)

**Company**: Synopsys
**Location**: Bengaluru, Karnataka
**Work arrangement**: onsite
**Experience**: mid
**Job type**: full-time
**Category**: Engineering
**Industry**: Technology
**Ticker**: SNPS
**Wikidata**: https://www.wikidata.org/wiki/Q2303478

**Apply**: https://careers.synopsys.com/job/bengaluru/asic-digital-verification-engineer-ethernet-ufs-unipro-usb-ip-verification/44408/103259314752?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/job/asic-digital-verification-engineer-ethernet-ufs-a8c29b97-8e8/

## Description

The Synopsys Digital IP R&D team is hiring experienced ASIC/IP Verification Engineers (2 to 5 years) to work on advanced connectivity protocols, including Ethernet / UFS / UniPro / USB / MPhy, across commercial, enterprise, and automotive applications.

You will be part of the Synopsys IP Verification R&D team at our Bangalore R&D Center, working closely with the RTL design team within a global team of expert Verification Engineers.

Key responsibilities:

- Contribute to end-to-end verification of subsystems with high-speed interconnect IPs, including one or more of controllers and Phy IP related to protocols such as Ethernet / UFS / UniPro / USB / MPhy, from test planning to coverage closure and sign-off

- Develop and use state-of-the-art verification environments for the Synopsys IP family of synthesizable cores, and perform verification tasks on these IP cores

- Understand compliance testing standards and build simulation-based compliance test suites

- Develop SystemVerilog/Verilog testbenches and test cases; run regressions, analyze coverage, and debug failures using methodologies such as UVM and formal verification

- Cover test planning, unit-level and system-level test environment coding, test case coding and debugging, Controller-PHY IP interoperability testing, and regression management

- Beyond traditional verification, you’ll have the opportunity to work with frontier AI models and build agentic workflows for verification, from automated testbench creation and test planning to coverage analysis and closure.

Requirements:

- Engineering degree / Post graduation (B.Tech / M.Tech) with 2–5 years of verification experience

- Hands on experience with coding in Verilog, System Verilog and methodology such as UVM

- Controller–PHY integration / interoperability simulation experience is a strong plus

- Prior experience in usage of industry standard VIP is a definite advantage

- Experience with SVA assertions, functional coverage, and coverage-driven verification

- Strong debug skills using Verdi (waveform + transaction/protocol-level analysis, RCA)

- Proficiency in one or more structured programming languages such as C, C++, Python.

- Experience building AI agents, agentic workflows, and AI-driven engineering automation will be a distinct advantage

- Strong analytical thinking, problem-solving ability, debugging skills, and attention to detail

- Ability to collaborate across design/architecture/validation teams and drive issues to resolution

- Effective written and oral communication is a must; Good interpersonal skills for working in a geographically distributed team

- High levels of motivation, curiosity, and a self-driven approach to learning

Benefits:

- Comprehensive medical and healthcare plans that work for you and your family

- In addition to company holidays, we have ETO and FTO Programs

- Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more

- Purchase Synopsys common stock at a 15% discount, with a 24 month look-back

- Save for your future with our retirement plans that vary by region and country

- Competitive salaries

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## Skills

### Required
- Verilog
- System Verilog
- UVM
- SVA assertions
- functional coverage
- coverage-driven verification
- C
- C++
- Python

### Nice to have
- Controller–PHY integration / interoperability simulation
- industry standard VIP
- AI agents
- agentic workflows
- AI-driven engineering automation

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Source: [Apply at careers.synopsys.com](https://careers.synopsys.com/job/bengaluru/asic-digital-verification-engineer-ethernet-ufs-unipro-usb-ip-verification/44408/103259314752?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)