# Digital Design Technical Leader for Silicon One Optics

**Company**: Cisco
**Experience**: senior
**Job type**: full-time
**Salary**: $166,300.00 to $238,300.00
**Category**: Engineering
**Industry**: Technology

**Apply**: https://cisco.wd5.myworkdayjobs.com/en-US/Cisco_Careers/job/Carlsbad-California-US/ASIC-Digital-Design-Tech-Lead_2025311?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_a83c9a10-198

## Description

The Silicon One team at Cisco creates innovative hardware platforms central to the AI era, powering core Switching, Routing, and Wireless products for organizations globally.

As a Digital Design Technical Leader for Silicon One Optics, you will architect the backbone of next-generation optical interconnects. You will own the full ASIC lifecycle and lead cross-functional engineering teams across digital, analog, firmware, and physical design.

Key responsibilities:

- Lead individual design contributions from pre-silicon RTL through GDS2 signoff and post-silicon bring-up for complex digital blocks and CPU subsystems.

- Translate top-level requirements into high-speed datapath and low-speed control plane block specifications.

- Independently simulate and debug complex design issues, sign off on verification coverage, and support the integration of SerDes and DSP IPs.

- Support synthesis, DFT, low-power design, and timing closure while developing automation scripts to process Quality of Results (QoR) metrics.

- Partner seamlessly with cross-functional teams to resolve technical design challenges and maintain system stability.

Minimum qualifications:

- Bachelors + 8 years of related experience, or Masters + 6 years of related experience, or PhD + 3 years of related experience.

- Prior digital design experience working with FSMs, CPU sub-systems, complex SoCs, and FPGA validation.

- Prior experience in managing the complete ASIC/SoC design flow.

- Prior experience with key bus and interface protocols (e.g., SPI, I2C, APB, AXI) as well as high-speed SerDes, Ethernet, and D2D PHY IP.

Preferred qualifications:

- End-to-End Silicon Lifecycle & Architecture: Prior experience leading the architecture and design of complex digital blocks and CPU subsystems from pre-silicon RTL to GDS2 signoff, through post-silicon FPGA prototyping, lab validation, and ATE bring-up.

- Specification & Microarchitecture Design: Prior experience developing top and block-level specifications for high-speed datapath and low-speed control planes.

- Verification, Simulation & IP Integration: Prior experience reviewing verification coverage metrics, independently debugging verification issues, supporting firmware-based verification/architecture, and integrating SerDes and DSP IP.

- Implementation, Backend & Automation: Hands-on experience with backend implementation activities.

- Cross-Functional Leadership: Prior experience collaborating across cross-functional engineering teams to resolve technical trade-offs and complex design issues.

The starting salary range for this position is $166,300.00 to $238,300.00.

## Skills

### Required
- digital design
- ASIC design flow
- high-speed SerDes
- Ethernet
- D2D PHY IP
- SPI
- I2C
- APB
- AXI
- FPGA validation

### Nice to have
- End-to-End Silicon Lifecycle & Architecture
- Specification & Microarchitecture Design
- Verification, Simulation & IP Integration
- Implementation, Backend & Automation
- Cross-Functional Leadership

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Source: [Apply at cisco.wd5.myworkdayjobs.com](https://cisco.wd5.myworkdayjobs.com/en-US/Cisco_Careers/job/Carlsbad-California-US/ASIC-Digital-Design-Tech-Lead_2025311?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)