# ASIC Clocks Verification Engineer

**Company**: NVIDIA
**Work arrangement**: hybrid
**Experience**: senior
**Job type**: full-time
**Salary**: $116,000 - $189,750 USD
**Category**: Engineering
**Industry**: Technology

**Apply**: https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/ASIC-Clocks-Verification-Engineer---New-College-Grad-2026_JR2027579?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_a2e8b4ac-4da

## Description

The GPU clocks group at NVIDIA is seeking an exceptional ASIC Clocks Verification Engineer. The team is responsible for crafting all aspects of GPU clocking, collaborating with the front design team to understand clocking requirements for the chip, and interacting with the floor-planning and back-end team to craft the physical floorplan of the chip.

**Key Responsibilities:**

- Collaborate with architects, ASIC designers, and verification engineers to verify high-frequency clock structures

- Engage with multiple teams to design the GPU clock structure, satisfying all architectural constraints

- Apply general verification principles to verify clock design

- Deliver clock information to SOC verification team, timing and DFT teams using Perl to improve productivity

- Collaborate with software and product groups to debug GPU clock silicon bugs in new products

- Understand and design clocking structures to overcome sub-micron design challenges

- Identify improvements in current design and propose new ways to improve efficiency in GPU clocking design

**Requirements:**

- Master's degree in Electrical Engineering (or equivalent experience)

- Practical experience with SystemVerilog and Universal Verification Method (UVM)

- Experience with Design Verification, Logic Design, and Logic Synthesis

- Strong coding skills in Python, Perl, or other industry-standard scripting languages

**Benefits:**

- Base salary range: $116,000 - $189,750 USD

- Equity and benefits package

## Skills

### Required
- SystemVerilog
- Universal Verification Method (UVM)
- Design Verification
- Logic Design
- Logic Synthesis
- Python
- Perl

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Source: [Apply at nvidia.wd5.myworkdayjobs.com](https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/ASIC-Clocks-Verification-Engineer---New-College-Grad-2026_JR2027579?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)