You will lead SerDes PHY IP projects that power the next generation of high-speed connectivity in everything from data centers to automotive systems. Responsibilities Manage end-to-end delivery of high-speed SerDes PHY IP projects from definition through tapeout and customer deployment Lead cross-functional project teams including design engineers, verification engineers, and layout specialists to execute against aggressive schedules Partner with R&D and Marketing to define project roadmaps, prioritize features, and align technical deliverables with market requirements Identify resource gaps, manage project risks, and resolve cross-team dependencies before they block progress Drive process improvements across the engineering organization, implementing best practices that reduce cycle time and improve quality Collaborate with Sales, Marketing, and Customer Support teams on pre-sales technical engagement and post-sales issue resolution Deliver regular status updates to executive leadership and customers, translating technical progress into business outcomes The Impact You Will Have Accelerate time-to-market for advanced SerDes IP that enables high-speed connectivity in AI, automotive, and data center applications Enable customers to meet increasingly complex design requirements with proven, high-quality IP that integrates cleanly into their SoCs Strengthen Synopsys' reputation as a trusted partner for mission-critical semiconductor IP through consistent on-time, on-spec delivery Improve engineering efficiency across the organization by identifying bottlenecks and implementing scalable processes that work across multiple projects Foster tighter collaboration between R&D, Marketing, Sales, and Customer Support, ensuring alignment from early concept through customer deployment Contribute directly to Synopsys' leadership position in high-speed interface IP, supporting customers building the next generation of smart, connected devices Mentor project leads and engineers on your team, building organizational capability in technical program management and cross-functional leadership Requirements Bachelor's degree in Electrical Engineering, Computer Engineering, or related field with 8+ years of relevant experience, or Master's/PhD with 6+ years Deep technical knowledge of IC design, ASIC development flows, and semiconductor IP integration, particularly in mixed-signal or SerDes domains Proven track record leading complex engineering projects in a high-tech environment, ideally in semiconductor IP or ASIC development Strong risk management and change management skills, with experience navigating technical uncertainty and scope changes without derailing schedules Excellent stakeholder management and communication skills, you can explain technical tradeoffs to executives and translate customer requirements into actionable engineering plans Experience with SerDes PHY IP, high-speed interface standards like PCIe, USB, or Ethernet is a strong plus Familiarity with project management methodologies and tools, whether Agile, Waterfall, or hybrid approaches tailored to hardware development
high-speed interface standards like PCIe, USB, or Ethernet