# Senior ASIC Design Verification Engineer

**Company**: Hewlett Packard Enterprise
**Work arrangement**: hybrid
**Experience**: senior
**Job type**: full-time
**Salary**: $147,000 - $279,000 per year in Colorado and $140,000 - $321,000 per year in Minnesota & Wisconsin
**Category**: Engineering
**Industry**: Technology

**Apply**: https://hpe.wd5.myworkdayjobs.com/en-US/Jobsathpe/job/Chippewa-Falls-Wisconsin-United-States-of-America/Senior-ASIC-Design-Verification-Engineer---Slingshot_1217462?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_a1c6a171-04d

## Description

In this Senior ASIC Design Verification Engineer role at Hewlett Packard Enterprise, you will be responsible for all phases of pre-silicon design verification. The role is hybrid, requiring you to work on average 2 days per week from an HPE office.

**Responsibilities:**

- Follow and help define the team's design verification methodology

- Develop SystemVerilog and UVM testbench components, including bus functional models that drive and monitor stimulus

- Plan and implement block and integration level scoreboards and checkers to verify functional behavior

- Write and analyze functional coverage, providing input to block level milestones

- Triage regression failures and identify logic bugs, while driving bug closure

- Apply scripting, automation, and AI-assisted and agentic tools to improve the speed and quality of the verification process

- Provide guidance and mentoring to less experienced staff members to set an example of VLSI design and development innovation and excellence

- Participate in and provide input on the process for selection of future technical leaders

- Drive VLSI innovation and integration of new technologies into projects and activities in the design organization

**Requirements:**

- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent

- 10+ years of experience in VLSI design, verification, or implementation

- Expert level knowledge of SystemVerilog and of OVM or UVM methodologies

- Expert level knowledge of programming and scripting languages, hardware description languages, electronic design automation (EDA), and/or FPGA tools

- Expert level analytical and problem solving skills

- Ability to excel in a distributed team environment

- Executive level written and verbal communication skills; mastery in English

**Preferred Qualifications:**

- Experience verifying high-speed networking, switching, or NIC ASICs

- Experience with agentic AI coding tools and workflows applied to verification

- Experience with Python, Perl, Tcl, or another scripting language in Linux development environments

- Experience working as part of a geographically distributed team

**What We Offer:**

- Comprehensive suite of benefits supporting physical, financial, and emotional wellbeing

- Investment in your career through specific programs to help you reach your career goals

- Unconditional inclusion and celebration of individual uniqueness

**Salary Range:** The expected salary/wage range for this position is $147,000 - $279,000 per year in Colorado and $140,000 - $321,000 per year in Minnesota & Wisconsin.

## Skills

### Required
- SystemVerilog
- UVM
- VLSI design
- verification
- scripting
- automation
- AI-assisted tools
- analytical skills
- problem solving skills
- English

### Nice to have
- high-speed networking
- switching
- NIC ASICs
- agentic AI coding tools
- Python
- Perl
- Tcl
- Linux development environments
- geographically distributed team

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Source: [Apply at hpe.wd5.myworkdayjobs.com](https://hpe.wd5.myworkdayjobs.com/en-US/Jobsathpe/job/Chippewa-Falls-Wisconsin-United-States-of-America/Senior-ASIC-Design-Verification-Engineer---Slingshot_1217462?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)