# Senior ASIC Physical Design Engineer, Netlisting

**Company**: NVIDIA
**Location**: Santa Clara
**Work arrangement**: onsite
**Experience**: senior
**Job type**: full-time
**Category**: Engineering
**Industry**: Technology

**Apply**: https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-ASIC-Physical-Design-Engineer--Netlisting_JR2010852-1?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_a01e3ea1-40b

## Description

We are seeking a motivated Senior ASIC Physical Design Engineer, Netlisting to join our dynamic and growing team. As a Senior ASIC Physical Design Engineer, you will drive physical design of high-frequency and low-power CPUs, GPUs, SoCs at block level, cluster level, and/or full chip level, with a focus on netlist-related aspects such as equivalence checking, asynchronous checking including clock domain crossing checks and MTBF analysis, logic synthesis, netlist quality checks, etc.

Your responsibilities will include:

- Driving physical design of high-frequency and low-power CPUs, GPUs, SoCs at block level, cluster level, and/or full chip level

- Focusing on netlist-related aspects such as equivalence checking, asynchronous checking including clock domain crossing checks and MTBF analysis, logic synthesis, netlist quality checks, etc.

- Helping in all aspects of physical design, such as driving timing convergence, timing constraints generation and management, and ECO generation and implementation

To be successful in this role, you will need:

- A Bachelor's degree in Electrical or Computer Engineering with 5+ years' experience or a Master's degree in Electrical or Computer Engineering with 3+ years' experience

- Expertise in logic equivalence checking/FV required from RTL to tapeout with industry-standard tools

- A deep understanding of hardware architecture and hands-on skills in RTL/logic design for timing closure

- Experience in clock-domain-crossing checking, MTBF analysis, either with industry-standard tools or in-house tools

- Background with logic synthesis at either block or full-chip level, at project execution and/or flow development

- Strong experience in full-chip/sub-chip Static Timing Analysis (STA), timing constraints generation and management, and timing convergence

- Expertise and in-depth knowledge of industry standard EDA tools in related fields

- Proficiency in programming and scripting languages, such as, Perl, TCL, Make, Python, etc.

If you have experience in logic synthesis and equivalence checking/FV, familiarity with industry tools and flow, strong hands-on debugging capability and problem-solving skills, and a background in DFT timing closure for various modes, you will stand out from the crowd.

## Skills

### Required
- logic equivalence checking/FV
- RTL/logic design for timing closure
- clock-domain-crossing checking
- MTBF analysis
- logic synthesis
- Static Timing Analysis (STA)
- timing constraints generation and management
- timing convergence
- industry standard EDA tools
- Perl
- TCL
- Make
- Python

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Source: [Apply at nvidia.wd5.myworkdayjobs.com](https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-ASIC-Physical-Design-Engineer--Netlisting_JR2010852-1?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)