# ASIC Design Verification Engineer

**Company**: Cisco
**Location**: San Jose, CA
**Work arrangement**: onsite
**Experience**: senior
**Job type**: full-time
**Salary**: $186,900.00 - $267,700.00
**Category**: Engineering
**Industry**: Technology

**Apply**: https://cisco.wd5.myworkdayjobs.com/en-US/Cisco_Careers/job/San-Jose-California-US/ASIC-Design-Verification-Engineer--Technical-Leader_2016782?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_9e97d974-994

## Description

You will be in the Silicon One development organization as an ASIC design verification engineer in San Jose, CA. You collaborate closely with verification engineers, designers, hardware and cross-functional teams to verify the ASIC in simulation, in emulation, and during ASIC bring-up.

Your Impact:

- Maintaining existing DV environments and enhancing them

- Construct test bench including scoreboard, agents, sequencers, and monitors for new blocks

- Write test plan, develop test cases, debug regression failures and drive to module verification closure

- Ensuring complete verification coverage through implementation and review of code and functional coverage

- Use AI tools to develop innovative methods and processes to improve quality of design verification.

Minimum Qualifications:

- Bachelor's with 8+ years or Master's degree with 6+ of relevant experience required; prior experience with System Verilog and UVM methodology

- Prior experience in verifying complex blocks, cluster, and/or top level for ASIC/SoC

- Prior experience building test benches from scratch, hands on experience with System Verilog constraints, structures and classes.

- Prior experience with functional coverage and constrained random DV environments.

- Scripting skills: Perl and/or Python scripting

Preferred Qualifications:

- Strong domain experience in one or more protocols is a plus – PCIe, CXL, Ethernet, AHB/AXI, DDR, MMU.

- Experience with Veloce/HAPS is a plus

- Formal verification (iev/vc formal) knowledge is a plus

The starting salary range posted for this position is $186,900.00 to $267,700.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.

## Skills

### Required
- System Verilog
- UVM methodology
- ASIC/SoC verification
- Perl
- Python

### Nice to have
- PCIe
- CXL
- Ethernet
- AHB/AXI
- DDR
- MMU
- Veloce/HAPS
- Formal verification

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Source: [Apply at cisco.wd5.myworkdayjobs.com](https://cisco.wd5.myworkdayjobs.com/en-US/Cisco_Careers/job/San-Jose-California-US/ASIC-Design-Verification-Engineer--Technical-Leader_2016782?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)