# Senior ASIC Post Silicon DFT Lead

**Company**: Cisco
**Location**: Austin, Texas
**Experience**: senior
**Job type**: full-time
**Salary**: $177,600.00 - $257,400.00
**Category**: Engineering
**Industry**: Technology

**Apply**: https://cisco.wd5.myworkdayjobs.com/en-US/Cisco_Careers/job/Austin-Texas-US/ASIC-Post-silicon-DFT-Technical-Leader_2028211?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_9de12f85-050

## Description

The Silicon One team at Cisco is looking for a Senior ASIC Post Silicon DFT Lead. You will work with the post-silicon product engineering team, Reliability, Board team, package team, functional test team, and system teams to understand and define post-silicon bringup to production roadmap and drive DFT requirements early in the design cycle.

As a lead of this team, you will also be involved in crafting groundbreaking next-generation networking chips. You will help lead the post-silicon process and quality process through the entire production phase from the DFT design side.

Responsibilities:

- Work with post-silicon product engineering team, Reliability, Board team, package team, functional test team, and system teams to understand and define post-silicon bringup to production roadmap

- Drive DFT requirements early in the design cycle

- Craft groundbreaking next-generation networking chips

- Lead the post-silicon process and quality process through the entire production phase from the DFT design side

Minimum Qualifications:

- Bachelor's or Master's Degree in Electrical or Computer Engineering

- At least 12 years of experience in post-silicon validation, hardware bring-up, Yield/reliability learnings, ramp acceleration, FA efficiency, and production scalability

- Experience working with DFT team & post-silicon validation from initial bringup to high-volume production

- Experience working with Gate-level simulation, debugging with VCS and other simulators

- Post-silicon validation and debug experience; Ability to work with ATE patterns, P1687

Preferred Qualifications:

- Verilog design experience - developing custom DFT logic & IP integration; familiarity with functional verification

- DFT CAD development - Test Architecture, Methodology, and Infrastructure

- Test Static Timing Analysis

Benefits:

- Medical, dental, and vision insurance

- 401(k) plan with a Cisco matching contribution

- Paid parental leave

- Short and long-term disability coverage

- Basic life insurance

- Paid time away (vacation, holidays, sick time)

- Optional 10 paid days per full calendar year to volunteer

Salary Range:

- $177,600.00 - $257,400.00 per year (U.S. and/or Canada locations)

## Skills

### Required
- Electrical Engineering
- Computer Engineering
- post-silicon validation
- hardware bring-up
- DFT
- Gate-level simulation
- VCS

### Nice to have
- Verilog design
- DFT CAD development
- Test Static Timing Analysis

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Source: [Apply at cisco.wd5.myworkdayjobs.com](https://cisco.wd5.myworkdayjobs.com/en-US/Cisco_Careers/job/Austin-Texas-US/ASIC-Post-silicon-DFT-Technical-Leader_2028211?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)