# Senior Power Integrity Co-Design Engineer

**Company**: NVIDIA
**Location**: Santa Clara, CA
**Experience**: senior
**Job type**: full-time
**Category**: Engineering
**Industry**: Technology

**Apply**: https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-Power-Integrity-Co-Design-Engineer_JR2018836-2?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_9d760494-0c0

## Description

The SCG Architecture team at NVIDIA is seeking a Senior Power Integrity Co-Design Engineer to lead the design and delivery of di/dt mitigation across silicon, package, board, and platform.

This role involves architecting voltage-noise mitigation across the full stack and collaborating with various teams to define product-level voltage noise targets.

Key responsibilities include:

- Architecting voltage-noise mitigation across silicon, package, board, and platform

- Co-designing noise features with multiple teams

- Defining product-level voltage noise targets and driving them to closure

- Building and owning the Sim-to-Si correlation methodology for noise

- Modeling and prototyping next-gen noise features

- Leading show-stopper noise bugs during bringup

Requirements:

- BS/MS/PhD in EE, CE, or related field

- 5+ years of experience in silicon power integrity, voltage noise, or PDN

- Deep expertise in di/dt analysis and mitigation, voltage droop, PDN design, transient noise, decap budgeting, or voltage regulator response

- Hands-on silicon experience with bringup, characterization, and correlation

- Strong Sim-to-Si correlation skills and system-level objectivity

- Ability to collaborate in a matrixed environment and drive decisions through multiple collaborators

Preferred qualifications:

- Patents or publications in power integrity, voltage noise, PDN, or di/dt mitigation

- Experience with groundbreaking GPU, CPU, or AI accelerator silicon

- Application of ML/AI to noise modeling, transient prediction, or feature optimization

- Multi-rail, multi-domain PDN ownership at SoC level

- Track record of codifying methodology into reusable workflows or tooling

## Skills

### Required
- power integrity
- voltage noise
- PDN design
- di/dt analysis
- Sim-to-Si correlation

### Nice to have
- ML/AI
- GPU
- CPU
- AI accelerator
- multi-rail PDN ownership

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Source: [Apply at nvidia.wd5.myworkdayjobs.com](https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-Power-Integrity-Co-Design-Engineer_JR2018836-2?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)