# ASIC Implementation Technical Lead

**Company**: Cisco
**Location**: Bangalore
**Experience**: senior
**Job type**: full-time
**Category**: Engineering
**Industry**: Technology

**Apply**: https://cisco.wd5.myworkdayjobs.com/en-US/Cisco_Careers/job/Bangalore-India/ASIC-DFT-Engineering-Technical-Leader---ATPG--MBIST--SSN--SCAN---12--years_2020223?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_9c5ab3c8-e02

## Description

Join Cisco's Silicon One development organization as an ASIC Implementation Technical Lead in Bangalore, India, focusing on Design-for-Test. You'll work with front-end RTL teams and backend physical design teams to understand chip architecture and drive DFT requirements. Your responsibilities include:

- Implementing Hardware Design-for-Test (DFT) features for ATE, in-system test, debug, and diagnostics

- Developing innovative DFT IP in collaboration with multi-functional teams

- Integrating and validating test logic in all phases of implementation and post-silicon validation flows

- Participating in creating innovative hardware DFT and physical design aspects for new silicon device models

- Crafting solutions and debugging with minimal mentorship

Requirements:

- Bachelor's or Master's degree in Electrical or Computer Engineering with 12+ years of experience

- Knowledge of latest innovative trends in DFT, test, and silicon engineering

- Experience with Jtag protocols, Scan and BIST architectures, and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime

- Verification skills, including System Verilog, Logic Equivalency checking, and validating test-timing of the design

- Experience working with gate-level simulation, debugging with VCS and other simulators

- Post-silicon validation and debug experience

- Strong verbal skills and ability to thrive in a multifaceted environment

- Scripting skills in Tcl, Python/Perl

Preferred qualifications:

- Verilog design experience

- DFT CAD development experience

- Test Static Timing Analysis experience

- Post-silicon validation using DFT patterns

## Skills

### Required
- DFT
- Jtag protocols
- Scan and BIST architectures
- EDA tools
- System Verilog
- Logic Equivalency checking
- Gate-level simulation
- Post-silicon validation
- Tcl
- Python/Perl

### Nice to have
- Verilog design
- DFT CAD development
- Test Static Timing Analysis
- Post-silicon validation using DFT patterns

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Source: [Apply at cisco.wd5.myworkdayjobs.com](https://cisco.wd5.myworkdayjobs.com/en-US/Cisco_Careers/job/Bangalore-India/ASIC-DFT-Engineering-Technical-Leader---ATPG--MBIST--SSN--SCAN---12--years_2020223?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)