# IP Design Technical Lead/ Staff ASIC RTL Design Engineer

**Company**: Synopsys
**Location**: Bengaluru, Karnataka, India
**Work arrangement**: onsite
**Experience**: staff
**Job type**: employee
**Category**: Engineering
**Industry**: Technology
**Ticker**: SNPS
**Wikidata**: https://www.wikidata.org/wiki/Q2303478

**Apply**: https://careers.synopsys.com/job/bengaluru/ip-design-technical-lead-staff-asic-rtl-design-engineer/44408/90581151808?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_9b235f6e-c09

## Description

We are seeking a passionate and forward-thinking digital design expert to join our team as an IP Design Technical Lead/ Staff ASIC RTL Design Engineer. As a key member of our team, you will be responsible for architecting and implementing state-of-the-art RTL designs for the DesignWare IP family, targeting commercial, enterprise, and automotive applications.

## What you'll do

- Architecting and implementing state-of-the-art RTL designs for the DesignWare IP family, targeting commercial, enterprise, and automotive applications.

- Translating standard and functional specifications into detailed micro-architectures and comprehensive design documentation for medium to high complexity features.

- Leading and contributing hands-on to RTL coding, synthesis, CDC analysis, debug, and test development tasks.

- Collaborating with global teams and engaging directly with customers to understand and refine specification requirements.

## What you need

- Bachelor’s or Master’s degree in Electrical Engineering, Electronics, VLSI, or related field.

- 4+ years of hands-on industry experience in ASIC RTL design, with a strong portfolio of completed projects.

- Deep expertise in data path and control path design, including experience with Reed Solomon FEC, BCH codes, CRC architectures, and MAC SEC engines.

- Proficiency in synthesizable Verilog/SystemVerilog, simulation tools, and design flows including lint, CDC, synthesis, and static timing analysis.

## Skills

### Required
- RTL design
- Verilog/SystemVerilog
- simulation tools
- design flows

### Nice to have
- data path and control path design
- Reed Solomon FEC
- BCH codes
- CRC architectures
- MAC SEC engines

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Source: [Apply at careers.synopsys.com](https://careers.synopsys.com/job/bengaluru/ip-design-technical-lead-staff-asic-rtl-design-engineer/44408/90581151808?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)