# ASIC Digital Design, Staff Engineer **Company**: Synopsys **Location**: Noida, Uttar Pradesh **Work arrangement**: onsite **Experience**: staff **Job type**: full-time **Category**: Engineering **Industry**: Technology **Ticker**: SNPS **Wikidata**: https://www.wikidata.org/wiki/Q2303478 **Apply**: https://careers.synopsys.com/job/noida/asic-digital-design-staff-engineer/44408/96590873120?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply **Canonical**: https://yubhub.co/jobs/job_9a148d24-77b ## Description Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. You will lead verification ownership for critical IP, defining strategy and driving execution with a team of verification engineers across Noida and global sites. You will build and evolve subsystem-level UVM testbenches in System Verilog, integrating RTL, behavioral models, and protocol checkers for complex multi-interface designs. You will write and debug advanced test scenarios, assertions, and checkers that catch the corner cases others miss, especially around DDR, HBM, PCIe, UCIe, Ethernet, or UALink protocols. Your responsibilities will include: - Lead verification ownership for critical IP, defining strategy and driving execution with a team of verification engineers across Noida and global sites - Build and evolve subsystem-level UVM testbenches in System Verilog, integrating RTL, behavioral models, and protocol checkers for complex multi-interface designs - Write and debug advanced test scenarios, assertions, and checkers that catch the corner cases others miss, especially around DDR, HBM, PCIe, UCIe, Ethernet, or UALink protocols - Define comprehensive verification test plans with clear coverage goals, track functional and code coverage metrics, and drive closure to signoff - Manage regression suites, debug simulation failures, perform root cause analysis, and ensure issues are resolved before they propagate downstream - Collaborate directly with RTL designers and architects to clarify specs, challenge assumptions, and ensure functional correctness from the start - Mentor verification engineers on UVM methodology, debugging techniques, and verification best practices, raising the bar across the team The impact you will have: - Catch critical design bugs early in IP that powers AI training chips, automotive SoCs, and cloud infrastructure, preventing costly silicon respins - Shape verification methodology and tooling standards that will be adopted across Synopsys IP teams globally, influencing how thousands of engineers verify silicon - Accelerate time to market for high-stakes customer programs by delivering verified, signoff-quality IP blocks on schedule - Build reusable, maintainable testbench infrastructure that other teams can leverage, multiplying your impact across product lines - Contribute to the technical growth of verification engineers in Noida, creating a stronger, more capable team for future programs - Help Synopsys maintain its leadership position in semiconductor IP by ensuring our verification quality sets the industry benchmark Requirements: - Bachelor's or Master's in Electronics Engineering, Electrical Engineering, or Computer Science, with 5+ years of hands-on ASIC or FPGA verification experience - Deep expertise building UVM-based testbenches in System Verilog for complex, multi-interface ASIC designs, not just maintaining existing environments but architecting new ones - Proven track record technically leading verification efforts, including defining test plans, driving coverage closure, and delivering IP to signoff - Strong experience with at least two of these protocols: DDR, HBM, PCIe, UCIe, Ethernet, or UALink, including writing protocol checkers and interface monitors - Demonstrated ability to write complex assertions, functional coverage models, and debug difficult simulation failures across large, integrated testbenches - Experience owning end-to-end verification deliverables, from initial planning through regression management, metrics closure, and final review signoff - Hands-on proficiency extracting, analyzing, and acting on verification metrics using industry-standard coverage tools and methodologies ## Skills ### Required - UVM - System Verilog - RTL - DDR - HBM - PCIe - UCIe - Ethernet - UALink --- Source: [Apply at careers.synopsys.com](https://careers.synopsys.com/job/noida/asic-digital-design-staff-engineer/44408/96590873120?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)