# Soc Engineer (synthesis/timing)

**Company**: Synopsys
**Location**: Ho Chi Minh City
**Work arrangement**: onsite
**Experience**: senior
**Job type**: employee
**Category**: Engineering
**Industry**: Technology
**Ticker**: SNPS
**Wikidata**: https://www.wikidata.org/wiki/Q2303478

**Apply**: https://careers.synopsys.com/job/ho-chi-minh-city/soc-engineer-synthesis-timing/44408/92181994832
**Canonical**: https://yubhub.co/jobs/job_989e07eb-cc7

## Description

Opening. Our team is looking for a SOC engineer to work on ASIC/SOC projects in Synopsys Ho Chi Minh City, District 7.

## What you'll do

Responsible for the development and implementation of System Design Solutions using Synopsys EDA tools and IP to solve customer problems as part of a service project team. Contributes to both turnkey projects and as a trusted advisor to customer design. Develop innovative solutions to problems with little guidance and implement them independently. Set task-level goals and consistently meet schedules. Works with other Synopsys teams including BU AEs and Sales to develop, broaden and deploy Tool and IP solutions.

- Synthesis

- LEC

- LDRC

- GCA

- STA

- PTPX

## What you need

- 6-12 years of related experience.

- Good of ASIC/SOC design, synthesis, timing closure.

- Familiar with Synthesis, LEC, STA flow.

- It’s a plus if you have experience in low-power, high-performance design, advanced nodes under 12nm.

- Knowledge of RTL, DFT, LDRC, GCA, VCLP, PTPX, IREM is advantageous.

- Familiar with scripting languages, such as TCL, Perl, Python.

- Good English/communication skills and willingness to work with customer.

- BS or MS with an EE or related major

## Skills

### Required
- Synthesis
- LEC
- STA
- PTPX

### Nice to have
- low-power
- high-performance design
- advanced nodes under 12nm
- RTL
- DFT
- LDRC
- GCA
- VCLP
- IREM
- TCL
- Perl
- Python