# Principal ASIC Verification Engineer

**Company**: Synopsys
**Location**: Munich
**Work arrangement**: onsite
**Experience**: senior
**Job type**: full-time
**Category**: Engineering
**Industry**: Technology
**Ticker**: SNPS
**Wikidata**: https://www.wikidata.org/wiki/Q2303478

**Apply**: https://careers.synopsys.com/job/munich/principal-asic-verification-engineer/44408/91377529600
**Canonical**: https://yubhub.co/jobs/job_98785e57-1a3

## Description

As a Principal ASIC Verification Engineer at Synopsys, you will be responsible for partnering with design teams to define verification requirements, developing test plans from specifications, and building and maintaining UVM testbenches and agents.

## What you'll do

- Partnering with design teams to define verification requirements

- Developing test plans from specifications

- Building and maintaining UVM testbenches and agents

## What you need

- B.Sc./M.Sc. in a relevant engineering field

- 10+ years in ASIC/UVM verification

## Skills

### Required
- SystemVerilog
- C
- Python
- TCL/Perl
- UVM
- SVA
- Formal verification

### Nice to have
- Interface IPs (PCIe, CXL)
- AI tools