# Principal ASIC Digital Design Engineer

**Company**: Synopsys
**Location**: Mississauga, Ontario, Canada
**Work arrangement**: onsite
**Experience**: senior
**Job type**: full-time
**Category**: Engineering
**Industry**: Technology
**Ticker**: SNPS
**Wikidata**: https://www.wikidata.org/wiki/Q2303478

**Apply**: https://careers.synopsys.com/job/mississauga/asic-digital-design-principal-engineer-14687/44408/91568840256
**Canonical**: https://yubhub.co/jobs/job_980acb3a-e35

## Description

As a Principal ASIC Digital Design Engineer, you will be responsible for designing and verifying advanced digital circuits for PAM-based SerDes PHY IP. Your expertise in high-speed serializer and data recovery circuits will position you as a key contributor to the next generation of PAM-based SerDes products.

## What you'll do

- Designing and verifying advanced digital circuits for PAM-based SerDes PHY IP, ensuring robust and high-performance mixed-signal solutions.

- Developing RTL code, modeling analog blocks, and crafting complex system-level testbenches in Verilog to validate functionality and performance.

## What you need

- Bachelor's or Master's degree in Electrical Engineering (BSEE or MSEE) with at least 10 years of industry experience in digital design and verification.

- Must be familiar with Verilog and VCS. Good knowledge of back-end synthesis tools DC/PT is required

- Must have knowledge of digital design methodologies, ATE production testing, DFT insertion, Synthesis constraints and flows

## Skills

### Required
- Verilog
- VCS
- digital design methodologies
- ATE production testing
- DFT insertion
- Synthesis constraints and flows

### Nice to have
- RTL coding
- modeling of analog blocks
- writing complex system-level test-benches in Verilog
- defining synthesis design constraints
- resolving STA issues
- gate-level simulation failures
- Clock/Reset domain crossing design constraints
- evaluating violations using CDC/RDC tools