# ASIC Designer

**Company**: Cisco
**Location**: San Jose, California
**Experience**: senior
**Job type**: full-time
**Salary**: $186,900.00 - $267,700.00
**Category**: Engineering
**Industry**: Technology

**Apply**: https://cisco.wd5.myworkdayjobs.com/en-US/Cisco_Careers/job/San-Jose-California-US/ASIC-Design-Technical-Lead--CPU-subsystems-_2028738?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/job/asic-designer-98097806-ef4/

## Description

The Silicon One team at Cisco is seeking an experienced ASIC designer to lead the architecture and design of complex CPU subsystems for next-generation high-performance networking switch ASICs.

You will use your expertise in all stages of ASIC development from specification and RTL design through post-silicon bring-up. You will collaborate closely with SDK, board-support package (BSP), and Network OS (NOS) software teams to define driver interfaces, register maps, and memory consistency models, while supporting early emulation and FPGA platforms.

Minimum Qualifications:

- Bachelor’s + 8 years of related experience, or Master’s + 6 years of related experience, or PhD + 3 years of related experience

- Prior experience with microarchitectural RISC-V, ARM or ARC processor ecosystems.

- Prior experience with on-chip interconnect fabrics (such as AXI, CHI, NoC).

- Prior experience with PCIe subsystems.

- Prior experience with ASIC/SoC design flow, including RTL development using SystemVerilog, pre-silicon verification, lint, CDC/RDC, synthesis/timing/constraints, implementation handoff, and post-silicon bring-up for SoC blocks.

Preferred Qualifications:

- Prior experience in leading CPU/SoC subsystem architecture or design for high-performance networking or data-center SoCs

- Prior experience with Boot, Security, Root of Trust (RoT), secure boot chains, and debug/trace infrastructure (such as CoreSight, RISC-V Debug).

The starting salary range for this position is $186,900.00 to $267,700.00.

Benefits include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance.

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## Skills

### Required
- RISC-V
- ARM
- ARC
- ASIC/SoC design
- SystemVerilog
- PCIe
- on-chip interconnect fabrics

### Nice to have
- CPU/SoC subsystem architecture
- Boot
- Security
- Root of Trust (RoT)
- CoreSight
- RISC-V Debug

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Source: [Apply at cisco.wd5.myworkdayjobs.com](https://cisco.wd5.myworkdayjobs.com/en-US/Cisco_Careers/job/San-Jose-California-US/ASIC-Design-Technical-Lead--CPU-subsystems-_2028738?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)