# Senior SOC Design Engineer

**Company**: NVIDIA
**Location**: Bengaluru
**Work arrangement**: onsite
**Experience**: senior
**Job type**: full-time
**Category**: Engineering
**Industry**: Technology

**Apply**: https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-SOC-Design-Engineer_JR2018209?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_96edb94e-46c

## Description

We are looking for a Senior SOC Design Engineer to join our team. As a Senior SOC Design Engineer, you will be responsible for driving SOC assembly and design chip level functions for Tegra SOCs. You will also be responsible for front-end design quality/correctness checks, reviews and driving those with multi-functional teams. You will work closely with chip management to set ASIC execution timelines & goals while directly interacting with System Architecture, unit-level ASIC, Physical Design, CAD, Package Design, DFT and other teams.

The ideal candidate will have a real passion for methodologies and automation solutions that enable SOC creation in the most optimized way. You will have a strong inclination in RTL integration and chip level front-end design, including padring, pinmuxing, SOC Assembly process, retiming etc. You will also have excellent analytical and problem-solving skills, experience in RTL design (Verilog), System-On-Chip design/implementation flow, and strong coding skills in Perl, Python, or other industry-standard scripting languages.

In this position, you will have the opportunity to build sophisticated Tegra SOCs and work closely with chip management to set ASIC execution timelines & goals. You will also be involved in defining and crafting methodologies that build more efficient and flexible SOCs in future.

## Skills

### Required
- RTL design (Verilog)
- System-On-Chip design/implementation flow
- Perl
- Python
- Scripting languages

### Nice to have
- Padring and fuse/floorsweep design experience
- SOC Verification, Synthesis, Physical design and DFT
- RTL Build flows and Makefiles

---

Source: [Apply at nvidia.wd5.myworkdayjobs.com](https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-SOC-Design-Engineer_JR2018209?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)